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www.latticesemi.com 1 5kvg_09 ispmach 5000vg family 3.3v in-system programmable superbig, superwide high density plds december 2001 data sheet tm tm tm features high density ? 768 to 1,024 macrocells ? 196 to 384 i/os sysclock? pll ? timing control ? multiply and divide factors between 1 and 32 ? clock shifting capability 3.5ns in 500ps steps ? multiple output frequencies ? external feedback capability for board-level clock deskew ?l vds/lvpecl clock input capability high speed logic implementation ? superwide 68-input logic block ? up to 160 product terms per output ? hierarchical routing structure provides fast inter- connect sysio? capability ?l vcmos 1.8, 2.5 and 3.3 ?l vttl ? sstl 2 (i & ii) ? sstl 3 (i & ii) ? ctt 3.3, ctt 2.5 ? hstl (i & iii) ? pci-x, pci 3.3 ? gtl+ ?a gp-1x ? 5v tolerance ? programmable drive strength ease of design ? product term sharing ? extensive clocking and oe capability easy system integration ? 3.3v power supply ? hot socketing ? input pull-up, pull-down or bus-keeper ? open drain capability ? slew rate control ? macrocell-based power management ? ieee 1149.1 boundary scan testable ? in-system programmable via ieee 1532 isc compliant interface ispmach 5000vg introduction the ispmach 5000vg represents the third generation of lattice?s superwide cpld architecture. through their wide 68-input blocks, these devices give signi - cantly improved speed performance for typical designs ov er architectures with fewer inputs. the ispmach 5000vg takes the unique bene ts of the superwide architecture and extends it to higher densi- ties referred to as superbig, by using the combination of an innovative product term architecture and a two- tiered hierarchical routing architecture. additionally, sysclock and sysio capabilities have been added to maximize system-level performance and integration. ta b le 1. ispmach 5000vg family selection guide ispmach 5768vg ispmach 51024vg macrocells 768 1,024 user i/o options 196/304 304/384 t pd (ns) 5.0 5.0 t s ? set-up with 0 hold (ns) 3.0 3.0 t co (ns) 4.4 4.4 f max (mhz) 178 178 supply voltage (v) 3.3v 3.3v pa c kage 256-ball fpbga 484-ball fpbga 484-ball fpbga 676-ball fpbga
lattice semiconductor ispmach 5000vg family data sheet 2 overview the ispmach 5000vg devices consist of multiple superwide 68-input, 32-macrocell generic logic blocks (glbs) interconnected by a tiered routing system. figure 1 shows the functional block diagram of the ispmach 5000vg. groups of four glbs, referred to as segments, are interconnected via a segment routing pool (srp). segments are interconnected via the global routing pool (grp.) together the glbs and the routing pools allow designers to create large designs in a single device without compromising performance. each glb has 68 inputs coming from the srp and contains 163 product terms. these product terms form groups of ve product term clusters, which feed the pt sharing array or the macrocell directly. the ispmach 5000vg allows up to 160 product terms to be connected to a single macrocell via the product term expanders and pt shar- ing array. the macrocell is designed to provide e xible clocking and control functionality with the capability to select between global, product term and block-level resources. the outputs of the macrocells are fed back into the switch matrices and, if required, the sysio cell. all i/os in the ispmach 5000vg family are sysios, which are split into four banks. each bank has a separate i/o power supply and reference voltage. the sysio cells allow operation with a wide range of today?s emerging inter- f ace standards. within a bank, inputs can be set to a variety of standards, providing the reference voltage require- ments of the chosen standards are compatible. within a bank, the outputs can be set to differing standards, providing the i/o power supply voltage and the reference voltage requirements of the chosen standard are compat- ible. support for this wide range of standards allows designers to achieve signi cantly higher board-level perfor- mance compared to the more traditional lvcmos standards. figure 1. functional block diagram pll0 pll1 glb v ccp0 v cco0 gclk0 v ref0 resetb goe1 goe2 toe tdi tdo tms tck v ccj i/o bank 0 i/o bank 3 i/o bank 1 i/o bank 2 gndp0 v ccp1 gndp1 glb glb glb global routing pool srp srp srp srp srp srp srp srp v cco1 gclk1 v ref1 v cco3 gclk3 v ref3 v cco2 gclk2 v ref2 glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb glb
lattice semiconductor ispmach 5000vg family data sheet 3 the ispmach5000vg devices also contain sysclock phase locked loops (plls) that provide designers with increased clocking e xibility. the plls can be used to synthesize new clocks for use on-chip or elsewhere within the system. they can also be used to deskew clocks, again both at the chip and system levels. a variable delay line capability further improves this and allows designers to retard or advance the clock in order to tune set-up and clock-to-out times for optimal results. the ispmach 5000vg family selection guide (table 1) details the key attributes and packages for the ispmach 5000vg devices. ispmach 5000vg architecture the ispmach 5000vg family of in-system programmable high density logic devices is based on segments con- taining four generic logic blocks (glbs) and a hierarchical routing pool (grp) structure interconnecting the seg- ments. a segment routing pool (srp) connects each glb in a segment allowing the maximum e xibility and speed. outputs from the glbs drive the segment routing pool (srp) and the global routing pool (grp). enhanced s witching resources are provided to allow signals in the segment routing pool to drive any or all the glbs in the segment. optimal switching is provided to allow all signals in the global routing pool to be routed to any or all srps. this mechanism allows fast, ef cient connections across the entire device. segment each segment contains four glbs and a segment routing pool (srp). each glb has 32 internal feedback outputs and 16 external feedback outputs, for a total of 48 outputs from each glb feeding the srp. the srp contains up to 384 signals, 48 from each glb and 192 from the grp, with full routing capability. this routing scheme maximizes the e xibility and speed of the device without sacri cing the routing. generic logic block each glb contains 32 macrocells and a fully populated, programmable and-array with 160 logic product terms and three control product terms. the glb has 68 inputs from the segment routing pool, which are available in both true and complement form for every product term. the three control product terms are used for shared reset, clock and output enable functions. figure 3 shows the structure of the glb from the macrocell perspective. this is referred to as a macrocell slice. there are 32 macrocell slices per glb. and-array the programmable and-array consists of 68 inputs and 163 output product terms. the 68 inputs from the srp are used to form 136 lines in the and-array (true and complement of the inputs). each line in the array can be con- nected to any of the 163 output product terms via a wired and. each of the 160 logic product terms feed the dual- or array with the remaining three control product terms feeding the shared pt clock, shared pt reset and shared pt oe. every set of ve product terms from the 160 logic product terms forms a product term cluster start- figure 2. segment clocks 4 glb segment routing p ool (srp) 48 68 48 48 68 48 68 68 48 48 192 f rom grp to grp to grp to grp clocks 4 to grp 48 48 clocks 4 clocks 4 glb glb glb
lattice semiconductor ispmach 5000vg family data sheet 4 ing with pt0. there is one product term cluster for every macrocell in the glb. in addition to the three control prod- uct terms, the rst, third, fourth and fth product terms of each cluster can be used as a ptoe (output macrocells only), pt clock, pt preset and pt reset, respectively. figure 4 is a graphical representation of the and-array. figure 3. macrocell slice figure 4. and-array from srp 68 speed/ power ptsa from n-7 to n+7 ptsa bypass pt oe to i/o block from i/o cell pt clock pt preset pt reset shared pt reset shared pt clock bclk0 bclk1 bclk2 bclk3 global reset clk en clk r/l d pr q and array dual-or array macrocell output to i/o block grp and srp pt0 pt1 cluster 0 pt2 pt3 pt4 in[0] in[66] in[67] note: indicates programmable fuse. pt160 pt161 pt162 shared cloc k shared reset shared oe pt156 pt157 pt158 pt159 pt155 cluster 31
lattice semiconductor ispmach 5000vg family data sheet 5 enhanced dual-or array to f acilitate logic functions requiring a very large number of product terms, the ispmach 5000vg architecture has been enhanced with an innovative product term expander capability. this capability is embedded in the dual-or array. the dual-or array consists of 64 or gates. there are two or gates per macrocell in the glb. these or gates are referred to as the expandable ptsa or gate and the ptsa-bypass or gate. the ptsa-bypass or gate receives its ve inputs from the combination of product terms associated with the prod- uct term cluster. the ptsa-bypass or gate feeds the macrocell directly for fast narrow logic. the expandable ptsa or gate receives ve inputs from the combination of product terms associated with the product term cluster. it also receives an additional input from the expanded ptsa or gate of the n-7 macrocell, where n is the number of the macrocell associated with the current or gate. the expandable ptsa or gate feeds the ptsa for sharing with other product terms and the n+7 expandable ptsa or gate. this allows cascading of multiple or gates for wide functions. there is a small timing adder for each level of expansion. figure 5 is a graphical representation of the enhanced dual-or array. figure 5. enhanced dual-or array from n-7 to n+7 f rom pt0 f rom pt1 f rom pt2 f rom pt3 f rom pt4 ptsa bypass to macrocell to i/o block to macrocell to macrocell to macrocell to ptsa pt oe pt clock pt preset pt reset n
lattice semiconductor ispmach 5000vg family data sheet 6 product term sharing array the product term sharing array (ptsa) consists of 32 inputs from the dual-or array (expandable ptsa or) and 32 outputs directly to the macrocells. each output is the or term of any combination of the seven expandable ptsa or terms connected to that output. every nth macrocell is connected to n-3, n-2, n-1, n, n+1, n+2 and n+3 ptsa or terms via a programmable connection. this wraps around the logic, macrocell 0 gets its logic from 29, 30, 31, 0, 1, 2, 3. the expandable ptsa or used in conjunction with the ptsa allows wide functions to be implemented easily and ef ciently. without using the expandable ptsa or capability, the greatest number of product terms that can be included in a single function with one pass of delay is 35. figure 6 shows the graphical representation of the ptsa. macrocell the 32 registered macrocells in the glb are driven by the 32 outputs from the ptsa or the ptsa bypass. each macrocell contains a programmable xor gate, a programmable register/latch ip- op and the necessary clocks and control logic to allow combinatorial or registered operation. the macrocells each have two outputs, which can be fed to the srp, grp and i/o cell. this dual or concurrent out- put capability from the macrocell gives ef cient use of the hardware resources. one output can be a registered function for example, while the other output can be an unrelated combinatorial function. a direct register input from the i/o cell facilitates ef cient use of the macrocell to construct high-speed input registers. macrocell registers can be clocked from one of several global or product term clocks available on the device. a glo- bal and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. reset and preset for the macrocell register is provided from both global and product term signals. the macrocell register can be programmed to operate as a d-type register or a d-type latch. figure 7 is a graphical rep- resentation of the ispmach 5000vg macrocell. figure 6. product term sharing array ptsa or 0 ptsa or 1 ptsa or 2 ptsa or 3 ptsa or 29 ptsa or 30 ptsa or 31 macrocell 0 macrocell 1 macrocell 2 macrocell 29 macrocell 30 macrocell 31
lattice semiconductor ispmach 5000vg family data sheet 7 figure 7. macrocell i/o cell the i/o cell of the ispmach 5000vg device provides a high degree of e xibility. it includes the sysio feature and an enhanced output enable mux for optimal performance both on- and off-chip. the sysio feature allows i/o cells to be con gured to different i/o standards, drive strengths and slew rates. the enhanced output enable mux pro- vides up to 14 different output enable choices per i/o cell. the i/o cell contains an output enable (oe) mux, a programmable tri-state output buffer, a programmable input b uffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-keeper latch. the i/o cell receives its input from its associated macrocell. the i/o cell has a feedback line to its associated mac- rocell and a direct path to the grp and srp. the output enable (oe) mux selects the oe signal per i/o cell. the inputs to the oe mux are the four shared ptoe signals, ptoe and the two goe signals. the oe mux also has the ability to choose either the true or inverse of each of these signals. the output of the oe mux goes through a logical and with the toe signal to allow easy tri-stating of the outputs for testing purposes. the four shared ptoe signals are derived from pt163 of each glb in the segment. the ptoe signal is derived from the rst product term in each macrocell cluster, which is directly routed to the oe mux. therefore, every i/o cell can have a different oe signal. figure 8 is a graphical representation of the i/o cell. ptsa bypass from i/o cell output to i/o block grp and srp pt clock f rom ptsa pt preset pt reset shared pt reset shared pt clock bclk0 bclk1 bclk2 bclk3 global reset clk en clk r/l d pr q
lattice semiconductor ispmach 5000vg family data sheet 8 figure 8. i/o cell sysio capability the ispmach 5000vg devices are divided into four sysio banks, where each bank is capable of supporting 14 dif- f erent i/o standards. each sysio bank has its own i/o supply voltage (v cco ) and reference voltage (v ref ) resources allowing each bank complete independence from the others. each i/o within a bank is individually con- gurable based on the v cco and v ref settings. table 2 lists the sysio standards with the typical values for v cco , v ref and v tt . ta b le 2. ispmach 5000vg supported i/o standards sysio standard v cco v ref v tt l vttl 3.3v n/a n/a l vcmos-3.3 3.3v n/a n/a l vcmos-2.5 2.5v n/a n/a l vcmos-1.8 1.8v n/a n/a pci 3.3 3.3v n/a n/a pci-x 3.3v n/a n/a a gp-1x 3.3v n/a n/a sstl3, class i & ii 3.3v 1.5v 1.5v sstl2, class i & ii 2.5v 1.25v 1.25v ctt 3.3 3.3v 1.5v 1.5v ctt 2.5 2.5v 1.25v 1.25v hstl, class i 1.5v 0.75v 0.75v hstl, class iii 1.5v 0.9v 1.5v gtl+ n/a 1.0v 1.5v l vpecl, differential 1 n/a n/a n/a l vds 1 n/a n/a n/a 1. lvds and lvpecl are only supported on the dedicated clock pins. shared (segment) ptoe 0 shared (segment) ptoe 1 shared (segment) ptoe 2 shared (segment) ptoe 3 ptoe goe0 goe1 toe v cco to all other i/os in bank v cco for this bank v ref to all other i/os in bank v ref dependent input buffer cmos/ttl input buffer (v ref independent) i/o pad gnd output buffer (v cco independent for open drain outputs) data output from macrocell data input to routing data input to macrocell + ?
lattice semiconductor ispmach 5000vg family data sheet 9 global clock pins have additional capabilities that allow for higher performance applications. two global clock pins can be paired together to create a single global clock pin that can interface with certain differential signals. the toe and jtag pins of the ispmach 5000vg device are the only pins that do not have sysio capabilities. these pins only support the lvttl and lvcmos standards. there are three classes of i/o interface standards that are implemented in the ispmach 5000vg devices. the rst is the unterminated, single-ended interface. it includes the 3.3v lvttl standard along with the 1.8v, 2.5v and 3.3v l vcmos interface standards. additionally, pci 3.3, pci-x and agp-1x are all subsets of this type of interface. the second type of interface implemented is the terminated, single-ended interface standard. this group of inter- f aces includes different versions of sstl and hstl interfaces along with ctt and gtl+. usage of these particular i/o interfaces requires the use of an additional vref signal. at the system level, a termination voltage, vtt, is also required. typically, an output will be terminated to vtt at the receiving end of the transmission line it is driving. the nal types of interfaces implemented are the differential standards lvds and lvpecl. these interfaces are implemented on clock pins only. when using one of the differential standards, a pair of global clock pins (gclk0 and gclk1 or gclk3 and gclk2) is combined to create a single clock signal. f or more information on the sysio capability, please refer to technical note tn1000: ispmach 5000vg sysio design and usage guidelines . glb clock distribution the ispmach 5000vg family has four dedicated clock input pins: gclk0-gclk3. glck0 and gclk3 can be routed through a pll circuit or routed directly to the internal clock nets. the internal clock nets (clk0-clk3) are directly related to the dedicated clock pins (see secondary clock divider exception when using the sysclock cir- cuit). these feed the glb clock multiplexes which generate the glb clock signals (bclk0-bclk3). the glb clock m ultiplexer allows a variety of true and complementary versions of the clocks to be used within the glb. each b lock clock can be the true or inverse of its associated global clock or the inverse of the adjacent global clock. figure 9 shows the clock distribution network. figure 9. clock distribution network sysclock plls global clock routing glb clock routing clock net pll0 clk_out0 sec_out0 vref0 clk0 clk1 gclk0 gclk1 i/o/clk_out0 clock net clock net pll1 clk_out1 sec_out1 clk3 clk2 gclk3 gclk2 i/o/clk_out1 clock net bclk0 bclk1 bclk2 bclk3 to macrocells to macrocells to macrocells to macrocells vref1 vref3 vref2
lattice semiconductor ispmach 5000vg family data sheet 10 sysclock pll the sysclock pll circuitry consists of phase-lock loops (plls) and the various dividers, reset and feedback signals associated with the plls. this feature gives the user the ability to synthesize clock frequencies and gener- ate multiple clock signals for routing within the device. furthermore, it can generate clock signals that are deskewed either at the board level or the device level. the ispmach 5000vg devices provide two pll circuits. pll0 receives its clock inputs from gclk 0 and provides outputs to clk 0 (clk 1 when using the secondary clock). pll1 operates with signals from gclk 3 and clk 3 (clk 2 when using the secondary clock). the pll outputs (clk_out) are routed via a dedicated net to a dedi- cated pad. further the buffers at these dedicated pads are regular i/o buffers that can select either the i/o macro- cell or the clk_out (clk_out0/clk_out1) signal. the clk_out nets are not routed through the grp. additionally, there are two sets of signals used for external control. each pll has a set of pll_rst, pll_fbk and pll_lock signals. figure 10 shows the ispmach 5000vg pll block diagram. figure 10. pll block diagram in order to facilitate the multiply and divide capabilities of the pll, each pll has dividers associated with it: m, n and k. the m divider is used to divide the clock signal, while the n divider is used to multiply the clock signal. the k divider is only used when a secondary clock output is needed. this divider divides the primary clock output and f eeds to a separate global clock net. the v divider is used to provide lower frequency output clocks, while maintain- ing a stable, high frequency output from the pll?s vco circuit. the pll also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. this operates by inserting delay on the input or feedback lines in 0.5ns increments from 0 to 3.5ns. for more information on the pll, please refer to technical note tn1003: ispmach 5000vg pll usage guidelines . po wer management the ispmach 5000vg devices provide unique power management controls. the devices have two power settings, high power and low power, on a per node basis. low power consumption is approximately 50% of high power con- sumption with a timing delay adder (tlp) to the routing delay of the low power node. each node can be con gured as either high power or low power. however, care should be taken when sharing product terms between nodes with different power settings. the ispmach 5000vg devices also have a power-off feature for unused product terms. by default, any product term that is not used is con gured as such. this allows the device to operate at minimal power consumption with- out affecting the timing of the design. for more information on power management, please refer to technical note tn1002: po w er estimation in ispmach 5000vg devices . sec_out clk_out pll_lock clk_in pll_rst pll_fbk input clock (m) divider post -scalar (v) divider vco and phase detector pro gramable delay secondary clock (k) divider f eedback loop (n) divider clock net clock net
lattice semiconductor ispmach 5000vg family data sheet 11 ieee 1149.1-compliant boundary scan testability all ispmach 5000vg devices have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri cation. in addition, these devices can be linked into a board-level serial scan path for more board-level testing. the test access port has its own sup- ply voltage and can operate with lvcmos3.3, 2.5 and 1.8v standards. sysio quick con guration to f acilitate the most ef cient board test, the physical nature of the i/o cells must be set before running any continu- ity tests. as these tests are fast, by nature, the overhead and time that is required for con guration of the i/os? physical nature should be minimal so that board test time is minimized. the ispmach 5000vg family of devices allows this by offering the user the ability to quickly con gure the physical nature of the sysio cells. this quick con- guration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. lat- tice's ispvm? system programming software can either perform the quick con guration through the pc parallel port, or can generate the ate or test vectors necessary for a third-party test system. ieee 1532-compliant in-system programming in-system programming of devices provides a number of signi cant bene ts including rapid prototyping, lower inventory levels, higher quality and the ability to make in- eld modi cations. all ispmach 5000vg devices provide in-system programming (isp tm ) capability through their boundary scan test access port. this capability has been implemented in a manner that ensures that the port remains compliant to the ieee 1532 standard. by using ieee 1532 as the communication interface through which isp is achieved, customers get the bene t of a standard, well- de ned interface. the ispmach 5000vg devices can be programmed across the commercial temperature and voltage range. the pc-based lattice software facilitates in-system programming of ispmach 5000vg devices. the software takes the jedec le output produced by the design implementation software, along with information about the scan chain, and creates a set of vectors used to drive the scan chain. the software can use these vectors to drive a scan chain via the parallel port of a pc. alternatively, the software can output les in formats understood by common auto- mated test equipment. this equipment can then be used to program ispmach 5000vg devices during the testing of a circuit board. security bit a programmable security bit is provided on the ispmach 5000vg devices as a deterrent to unauthorized copying of the array con guration patterns. once programmed, this bit prevents readback of the programmed pattern by a device programmer, securing proprietary design from competitors. the security bit also prevents programming and veri cation. the entire device must be erased in order to erase the security bit. hot socketing the ispmach 5000vg devices are well suited for those applications that require hot socketing capability. hot sock- eting a device requires that the device, when powered down, can tolerate active signals on the i/os and inputs with- out being damaged. additionally, it requires that the effects of the powered-down device be minimal on active signals. density migration the ispmach 5000 family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is possible to shift a lower utilization design tar- geted for a high density device to a lower density device. however, the exact details of the nal resource utilization will impact the likely success in each case.
lattice semiconductor ispmach 5000vg family data sheet 12 absolute maximum ratings 1, 2, 3 supply voltage (v cc ). . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.4v pll supply voltage (v ccp ) . . . . . . . . . . . . . . . . . . . . -0.5 to 5.4v output supply voltage (v cco ). . . . . . . . . . . . . . . . . . -0.5 to 5.4v input voltage applied 4 . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.6v tr i-state output voltage applied. . . . . . . . . . . . . . . . . -0.5 to 5.6v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c j unction temperature (tj) with power applied . . . . . -55 to 130 c 1. stress above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied. 2. compliance with lattice thermal management document is required. 3. all voltages referenced to gnd. 4. overshoot and undershoot of -2v to (v ih (max)+2) volts is permitted for a duration of < 20ns. recommended operating conditions erase reprogram speci cations hot socketing characteristics 1,2,3 symbol parameter min max units v cc supply voltage 3.0 3.6 v v ccp supply voltage for pll block 3.0 3.6 v v ccj supply voltage for ieee1149.1 test access port 1.65 3.6 v tj (commercial) junction commercial operation 0 90 c tj (industrial) junction industrial operation -40 105 c note: v ccj must be set in appropriate range to be compatible with desired lvcmos standard. p arameter min max units erase/reprogram cycle 1000 ? cycles symbol parameter condition min typ max units i dk input or i/o leakage current 0 v in v ih (max) ? ? +/-100 a v ih (max) v in 5.5v ? ? +/-100 a 1. insensitive to sequence of v cc and v cco . however, assumes monotonic rise / fall rates for v cc and v cco . 2. lvttl, lvcmos only 3. 0 < v cc v cc (max), 0 < v cco v cco (max)
lattice semiconductor ispmach 5000vg family data sheet 13 dc electrical characteristics over recommended operating conditions symbol parameter condition min typ max units i il , i ih 1 input or i/o leakage current 0v v in v ih (max) ? ? +/-10 a i pu 2 i/o weak pull-up resistor current 0 v in 0.7 v cco v cco = 3.3 -30 ? -150 a v cco = 2.5 -20 ? -150 a v cco = 1.8 -10 ? -150 a i pd 2 i/o weak pull-down resistor current v il (max) v in v ih (max) 30 ? 150 a i bhls 2 bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs 2 bus hold high sustaining current v in = 0.7 v cco v cco = 3.3 -30 ? ? a v cco = 2.5 -20 ? ? a v cco = 1.8 -10 ? ? a i bhlo 2 bus hold low overdrive current 0v v in v ih (max) ? ? 150 a i bhho 2 bus hold high overdrive current 0v v in v ih (max) ? ? -150 a i cc 3, 4, 5 operating power supply current v cc = 3.3v ? 380 ? ma v bht bus hold trip points v il (max) ? v ih (min) v c 1 i/o capacitance 3 v cc = 3.3v, v io = 0 to v ih (max) ?10 ?pf v cco = 3.3v, 2.5, 1.8, 1.5 c 2 clock capacitance 3 v cc = 3.3v, v io = 0 to v ih (max) ?10? pf v cco = 3.3v, 2.5, 1.8, 1.5 c 3 global input capacitance 3 v cc = 3.3v, v io = 0 to v ih (max) ?10? pf v cco = 3.3v, 2.5, 1.8, 1.5 1. input or i/o leakage current is measured with the pin con gured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. only available for lvcmos and lvttl standards. 3. t a = 25 c, f = 1.0mhz. 4. device con gured with 16-bit counters. 5. i cc varies with speci c device con guration and operating frequency.
lattice semiconductor ispmach 5000vg family data sheet 14 sysio recommended operating conditions 2 standard v cco (v) v ref (v) min max min max l vcmos 3.3 1 3.0 3.6 ? ? l vcmos 2.5 2.3 2.7 ? ? l vcmos 1.8 1.65 1.95 ? ? l vttl 3.0 3.6 ? ? pci 3.3 3.0 3.6 ? ? pci-x 3.0 3.6 ? ? a gp-1x 3.15 3.45 ? ? sstl 2 2.3 2.7 1.15 1.35 sstl 3 3.0 3.6 1.3 1.7 ctt 3.3 3.0 3.6 1.35 1.65 ctt 2.5 2.3 2.7 1.35 1.65 hstl 1.4 1.6 0.68 0.9 gtl+ 1.4 3.6 0.882 1.122 1. software default setting. 2. typical values for v cco and v ref are the average of the min and max values.
lattice semiconductor ispmach 5000vg family data sheet 15 sysio dc electrical characteristics over recommended operating conditions sysio differential input dc electrical characteristics and operating conditions standard v il v ih v ol max (v) v oh min (v) i ol 2 (ma) i oh 2 (ma) min (v) max (v) min (v) max (v) l vcmos 3.3 1 -0.3 0.8 2.0 5.5 0.4 2.4 20 -20 l vcmos 3.3 -0.3 0.8 2.0 5.5 0.4 2.4 16, 12 8, 5.33, 4 -16, -12, -8, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 l vttl -0.3 0.8 2.0 5.5 0.4 2.4 20 -20 0.2 v cco - 0.2 0.1 -0.1 l vcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v cco - 0.4 16, 12, 8, 5.33, 4 -16, -12, -8, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 l vcmos 1.8 -0.3 0.35v cco 0.65v cco 3.6 0.4 v cco -0.4 12, 8, 5.33, 4 -12, -8, -5.33, -4 0.2 v cco - 0.2 0.1 -0.1 pci 3.3 -0.3 0.3v cco 0.5v cco 3.6 0.1v cco 0.9v cco 1.5 -0.5 pci-x -0.3 0.35v cco 0.5v cco 3.6 0.1v cco 0.9v cco 1.5 -0.5 a gp-1x -0.3 0.3v cco 0.5v cco 3.6 0.1v cco 0.9v cco 1.5 -0.5 sstl3 class i -0.3 v ref -0.2 v ref +0.2 3.6 0.7 v cco -1.1 8 -8 sstl3 class ii -0.3 v ref -0.2 v ref +0.2 3.6 0.5 v cco -0.9 16 -16 sstl2 class i -0.3 v ref -0.18 v ref +0.18 3.6 0.54 v cco -0.62 7.6 -7.6 sstl2 class ii -0.3 v ref -0.18 v ref +0.18 3.6 0.35 v cco -0.43 15.2 -15.2 ctt 3.3 -0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.4 v ref +0.4 8 -8 ctt 2.5 -0.3 v ref -0.2 v ref +0.2 3.6 v ref -0.4 v ref +0.4 8 -8 hstl class i -0.3 v ref -0.1 v ref +0.1 3.6 0.4 v cco -0.4 8 -8 hstl class iii -0.3 v ref -0.1 v ref +0.1 3.6 0.4 v cco -0.4 24 -8 gtl+ -0.3 v ref -0.2 v ref +0.2 3.6 0.6 n/a 36 n/a 1. software default setting 2. the average dc current drawn by i/os between adjacent bank gnd connections, or between the last gnd in an i/o bank and the e nd of the i/o bank, as shown in the logic signals connection table, shall not exceed 96ma. symbol parameter test conditions min max v inp . v inm l vds input voltage ? 0 2.4 v thd l vds differential input threshold ? 100mv ? v il l vpecl input voltage low v cc = 3.0 to 3.6v v cc -1.81 v cc -1.48 v cc = 3.3v 1.49v 1.83v v ih l vpecl input voltage high v cc = 3.0 to 3.6v v cc -1.17 v cc -0.88 v cc = 3.3v 2.14v 2.42v
lattice semiconductor ispmach 5000vg family data sheet 16 ispmach 5768vg external switching characteristics over recommended operating conditions p arameter description 1,2,3 -5 -75 -10 -12 units min max min max min max min max t pd data propagation delay, 5-pt bypass ? 5.0 ? 7.5 ? 10.0 ? 12.0 ns t pd_ptsa data propagation delay, intrasegment path ? 6.0 ? 9.0 ? 11.5 ? 13.5 ns t pd_global data propagation delay, intersegment path ? 6.5 ? 9.75 ? 13.0 ? 16.0 ns t s glb register setup time before clock, 5-pt bypass 3.0 ? 5.0 ? 7.5 ? 9.3 ? ns t s_ptsa glb register setup time before clock 3.0 ? 6.0 ? 8.5 ? 10.0 ? ns t sir glb register setup time before clock, input register path 2.8 ? 3.0 ? 4.0 ? 5.0 ? ns t h glb register hold time before clock, 5-pt b ypass 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t h_ptsa glb register hold time before clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t hir glb register hold time before clock, input reg. path 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t co glb register clock-to-output delay ? 4.4 ? 5.0 ? 6.0 ? 7.0 ns t r external reset pin to output delay ? 6.5 ? 9.0 ? 10.0 ? 10.9 ns t rw external reset pulse duration 4.0 ? 6.0 ? 8.0 ? 9.5 ? ns t lptoe/dis input to output local product term output enable/disable ? 7.0 ? 9.75 ? 11.5 ? 13.4 ns t sptoe/dis input to output segment product term output enable/disable ? 8.0 ? 11.25 ? 17.5 ? 20.4 ns t goe/dis global oe input to output enable/disable ? 6.2 ? 7.5 ? 8.85 ? 10.0 ns t cw global clock width, high or low 1.6 ? 2.75 ? 3.6 ? 4.3 ? ns t gw global gate width low (for low transparent) or high (for high transparent) 1.8 ? 2.75 ? 3.6 ? 4.3 ? ns t wir input register clock width, high or low 1.8 ? 2.75 ? 3.6 ? 4.3 ? ns t skew clock-to-out skew, block level ? 0.25 ? 0.35 ? 0.45 ? 0.55 ns clock-to-out skew, segment level ? 0.4 ? 0.5 ? 0.6 ? 0.7 ns f max 4 clock frequency with internal feedback 178.6 ? 117.0 ? 87.0 ? 73.0 ? mhz f max (ext.) clock frequency with external feedback, 1/ (t s_ptsa + t co ) 135.1 ? 90.9 ? 69.0 ? 58.8 ? mhz f max (tog.) clock frequency max toggle 312.5 ? 181.0 ? 138.0 ? 116.0 ? mhz timing v.1.20 1. timing numbers are based on default lvcmos 3.3 i/o buffers. use timing adjusters provided to calculate timing for other stand ards. 2. measured using standard switching circuit, assuming segment and global routing loading of 1, worst case ptsa loading and 1 ou tput s witching. 3. pulse widths and clock widths less than minimum will cause unknown behavior. 4. standard 16-bit counter using srp feedback.
lattice semiconductor ispmach 5000vg family data sheet 17 ispmach 51024vg external switching characteristics over recommended operating conditions p arameter description 1,2,3 -5 -75 -10 -12 units min max min max min max min max t pd data propagation delay, 5-pt bypass ? 5.0 ? 7.5 ? 10.0 ? 12.0 ns t pd_ptsa data propagation delay, intrasegment path ? 6.0 ? 9.0 ? 11.5 ? 13.5 ns t pd_global data propagation delay, intersegment path ? 6.5 ? 9.75 ? 13.0 ? 16.0 ns t s glb register setup time before clock, 5-pt bypass 3.0 ? 5.0 ? 7.5 ? 9.3 ? ns t s_ptsa glb register setup time before clock 3.0 ? 6.0 ? 8.5 ? 10.0 ? ns t sir glb register setup time before clock, input register path 2.8 ? 3.0 ? 4.0 ? 5.0 ? ns t h glb register hold time before clock, 5-pt b ypass 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t h_ptsa glb register hold time before clock 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t hir glb register hold time before clock, input reg. path 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns t co glb register clock-to-output delay ? 4.4 ? 5.0 ? 6.0 ? 7.0 ns t r external reset pin to output delay ? 6.5 ? 9.0 ? 10.0 ? 10.9 ns t rw external reset pulse duration 4.0 ? 6.0 ? 8.0 ? 9.5 ? ns t lptoe/dis input to output local product term output enable/disable ? 7.0 ? 9.75 ? 11.5 ? 13.4 ns t sptoe/dis input to output segment product term output enable/disable ? 8.0 ? 11.25 ? 17.5 ? 20.4 ns t goe/dis global oe input to output enable/disable ? 6.2 ? 7.5 ? 8.85 ? 10.0 ns t cw global clock width, high or low 1.6 ? 2.75 ? 3.6 ? 4.3 ? ns t gw global gate width low (for low transparent) or high (for high transparent) 1.8 ? 2.75 ? 3.6 ? 4.3 ? ns t wir input register clock width, high or low 1.8 ? 2.75 ? 3.6 ? 4.3 ? ns t skew clock-to-out skew, block level ? 0.25 ? 0.35 ? 0.45 ? 0.55 ns clock-to-out skew, segment level ? 0.4 ? 0.5 ? 0.6 ? 0.7 ns f max 4 clock frequency with internal feedback 178.6 ? 117.0 ? 87.0 ? 73.0 ? mhz f max (ext.) clock frequency with external feedback, 1/ (t s_ptsa + t co ) 135.1 ? 90.9 ? 69.0 ? 58.8 ? mhz f max (tog.) clock frequency max toggle 312.5 ? 181.0 ? 138.0 ? 116.0 ? mhz timing v.1.10 1. timing numbers are based on default lvcmos 3.3 i/o buffers. use timing adjusters provided to calculate timing for other stand ards. 2. measured using standard switching circuit, assuming segment and global routing loading of 1, worst case ptsa loading and 1 ou tput s witching. 3. pulse widths and clock widths less than minimum will cause unknown behavior. 4. standard 16-bit counter using srp feedback.
lattice semiconductor ispmach 5000vg family data sheet 18 timing model the task of determining the timing through the ispmach 5000vg family, like any cpld, is relatively simple. the timing model provided in figure 11 shows the speci c delay paths. once the implementation of a given function is determined either conceptually or from the software report le, the delay path of the function can easily be deter- mined from the timing model. the lattice design tools report the timing delays based on the same timing model for a particular design. note that the internal timing parameters are given for reference only, and are not tested. the e xternal timing parameters are tested and guaranteed for every device. for more information on the timing model and usage, please refer to technical note tn1001: ispmach 5000vg timing model design and usage guidelines. figure 11. ispmach 5000vg timing model in t in t ioi out sclk f rom feedback rst oe f eedbac k italicized items are o p tional dela y adders t inreg t route t pdb t pdi t fbk t buf t en t dis t ioo data mc reg c .e. s/r q t ptsa t ptclk t bclk t ptsr t bsr t sptoe t ptoe t grp t blk t exp t lp t pll_delay t pll_sec_delay t gclk t rst t goe t ioi t ioi t ioi t gclk_in
lattice semiconductor ispmach 5000vg family data sheet 19 ispmach 5768vg internal timing parameters over recommended operating conditions p arameter description -5 -75 -10 -12 units min max min max min max min max in/out delays t in input buffer delay ? 0.65 ? 0.95 ? 1.25 ? 1.40 ns t gclk_in global clock input buffer delay ? 0.65 ? 0.95 ? 1.25 ? 1.40 ns t goe global oe pin delay ? 4.05 ? 5.00 ? 6.00 ? 7.00 ns t buf delay through output buffer ? 1.15 ? 1.50 ? 1.75 ? 1.90 ns t en output enable time ? 2.15 ? 2.50 ? 2.85 ? 3.00 ns t dis output disable time ? 2.15 ? 2.50 ? 2.85 ? 3.00 ns t rstb global resetbar pin delay ? 4.60 ? 6.50 ? 7.00 ? 7.50 ns routing delays t r oute delay through srp ? 2.80 ? 4.20 ? 5.65 ? 6.90 ns t ptsa product term sharing array delay ? 0.40 ? 1.85 ? 2.35 ? 2.50 ns t pdb 5-pt bypass propagation delay ? 0.40 ? 0.85 ? 1.35 ? 1.80 ns t pdi macrocell propagation delay ? 1.00 ? 0.50 ? 0.50 ? 0.80 ns t inreg input buffer to macrocell register delay ? 3.00 ? 3.05 ? 3.50 ? 4.40 ns t fbk internal feedback delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t gclk global clock tree delay ? 0.85 ? 0.70 ? 0.55 ? 0.65 ns t pll_delay programmable pll delay increment ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns t pll_sec_delay additional delay when using secondary pll output ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns t grp global routing pool delay ? 1.50 ? 2.25 ? 3.00 ? 4.00 ns register/latch delays t s d-register setup time 0.65 ? 0.65 ? 1.05 ? 1.25 ? ns t s_pt d-register setup time with pt clock 0.65 ? 0.65 ? 1.05 ? 1.25 ? ns t h d-register hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t st t -register setup time 1.15 ? 1.15 ? 1.55 ? 1.75 ? ns t st_pt t -register setup time with pt clock 1.15 ? 1.15 ? 1.55 ? 1.75 ? ns t ht t -register hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t coi register clock to output/feedback mux time ? 1.75 ? 1.85 ? 2.45 ? 3.05 ns t ces clock enable setup time 2.60 ? 3.90 ? 5.05 ? 5.95 ? ns t ceh clock enable hold time 0.60 ? 0.90 ? 1.20 ? 1.45 ? ns t sl latch setup time 2.80 ? 4.20 ? 5.50 ? 6.60 ? ns t sl_pt latch setup time with pt clock 2.80 ? 4.20 ? 5.50 ? 6.60 ? ns t hl latch hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t goi latch gate to output/feedback mux time ? 1.75 ? 2.50 ? 3.50 ? 4.50 ns t pdli propagation delay through transparent latch to output/feedback mux ? 2.40 ? 3.50 ? 4.00 ? 4.50 ns t sri asynchronous reset or set to output/feedback mux delay ? 0.75 ? 1.00 ? 1.25 ? 1.50 ns t srr asynchronous reset or set recovery delay ? 1.00 ? 1.50 ? 2.00 ? 2.50 ns control delays t bclk glb pt clock delay ? 3.10 ? 4.65 ? 6.00 ? 7.00 ns t ptclk macrocell pt clock delay ? 3.00 ? 4.50 ? 6.00 ? 7.00 ns
lattice semiconductor ispmach 5000vg family data sheet 20 t bsr block pt set/reset delay ? 2.00 ? 3.00 ? 4.00 ? 4.80 ns t ptsr macrocell pt set/reset delay ? 2.00 ? 3.00 ? 4.00 ? 4.80 ns t sptoe segment pt oe delay ? 2.40 ? 3.60 ? 7.75 ? 9.10 ns t ptoe macrocell pt oe delay ? 1.40 ? 2.10 ? 1.75 ? 2.10 ns notes: timing v.1.20 1. internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for further de tails. 2. t pll_delay is the unit increment by which the clock signal can be incremented. the pll can adjust the clock signal by up to 3.5ns in eith er direction in units of 0.5ns for each step. ispmach 51024vg internal timing parameters over recommended operating conditions p arameter description -5 -75 -10 -12 units min max min max min max min max in/out delays t in input buffer delay ? 0.65 ? 0.95 ? 1.25 ? 1.40 ns t gclk_in global clock input buffer delay ? 0.65 ? 0.95 ? 1.25 ? 1.40 ns t goe global oe pin delay ? 4.05 ? 5.00 ? 6.00 ? 7.00 ns t buf delay through output buffer ? 1.15 ? 1.50 ? 1.75 ? 1.90 ns t en output enable time ? 2.15 ? 2.50 ? 2.85 ? 3.00 ns t dis output disable time ? 2.15 ? 2.50 ? 2.85 ? 3.00 ns t rstb global resetbar pin delay ? 4.60 ? 6.50 ? 7.00 ? 7.50 ns routing delays t r oute delay through srp ? 2.80 ? 4.20 ? 5.65 ? 6.90 ns t ptsa product term sharing array delay ? 0.40 ? 1.85 ? 2.35 ? 2.50 ns t pdb 5-pt bypass propagation delay ? 0.40 ? 0.85 ? 1.35 ? 1.80 ns t pdi macrocell propagation delay ? 1.00 ? 0.50 ? 0.50 ? 0.80 ns t inreg input buffer to macrocell register delay ? 3.00 ? 3.05 ? 3.50 ? 4.40 ns t fbk internal feedback delay ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns t gclk global clock tree delay ? 0.85 ? 0.70 ? 0.55 ? 0.65 ns t pll_delay programmable pll delay increment ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns t pll_sec_delay additional delay when using secondary pll output ? 0.60 ? 0.60 ? 0.60 ? 0.60 ns t grp global routing pool delay ? 1.50 ? 2.25 ? 3.00 ? 4.00 ns register/latch delays t s d-register setup time 0.65 ? 0.65 ? 1.05 ? 1.25 ? ns t s_pt d-register setup time with pt clock 0.65 ? 0.65 ? 1.05 ? 1.25 ? ns t h d-register hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t st t -register setup time 1.15 ? 1.15 ? 1.55 ? 1.75 ? ns t st_pt t -register setup time with pt clock 1.15 ? 1.15 ? 1.55 ? 1.75 ? ns t ht t -register hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t coi register clock to output/feedback mux time ? 1.75 ? 1.85 ? 2.45 ? 3.05 ns ispmach 5768vg internal timing parameters (continued) over recommended operating conditions p arameter description -5 -75 -10 -12 units min max min max min max min max
lattice semiconductor ispmach 5000vg family data sheet 21 t ces clock enable setup time 2.60 ? 3.90 ? 5.05 ? 5.95 ? ns t ceh clock enable hold time 0.60 ? 0.90 ? 1.20 ? 1.45 ? ns t sl latch setup time 2.80 ? 4.20 ? 5.50 ? 6.60 ? ns t sl_pt latch setup time with pt clock 2.80 ? 4.20 ? 5.50 ? 6.60 ? ns t hl latch hold time 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns t goi latch gate to output/feedback mux time ? 1.75 ? 2.50 ? 3.50 ? 4.50 ns t pdli propagation delay through transparent latch to output/feedback mux ? 2.40 ? 3.50 ? 4.00 ? 4.50 ns t sri asynchronous reset or set to output/feedback mux delay ? 0.75 ? 1.00 ? 1.25 ? 1.50 ns t srr asynchronous reset or set recovery delay ? 1.00 ? 1.50 ? 2.00 ? 2.50 ns control delays t bclk glb pt clock delay ? 3.10 ? 4.65 ? 6.00 ? 7.00 ns t ptclk macrocell pt clock delay ? 3.00 ? 4.50 ? 6.00 ? 7.00 ns t bsr block pt set/reset delay ? 2.00 ? 3.00 ? 4.00 ? 4.80 ns t ptsr macrocell pt set/reset delay ? 2.00 ? 3.00 ? 4.00 ? 4.80 ns t sptoe segment pt oe delay ? 2.40 ? 3.60 ? 7.75 ? 9.10 ns t ptoe macrocell pt oe delay ? 1.40 ? 2.10 ? 1.75 ? 2.10 ns notes: timing v.1.10 1. internal timing parameters are not tested and are for reference only. refer to timing model in this data sheet for further de tails. 2. t pll_delay is the unit increment by which the clock signal can be incremented. the pll can adjust the clock signal by up to 3.5ns in eith er direction in units of 0.5ns for each step. ispmach 51024vg internal timing parameters (continued) over recommended operating conditions p arameter description -5 -75 -10 -12 units min max min max min max min max
lattice semiconductor ispmach 5000vg family data sheet 22 ispmach 5768vg timing adders adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max t bla t r oute glb loading adder ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns t exp t ptsa pt expander adder ? 1.5 ? 2.0 ? 2.5 ? 2.5 ns t lp t r oute low power adder ? 1.5 ? 1.5 ? 1.5 ? 1.5 ns t ioi input adders l vcmos18_in t in , t gclk_in , t rstb , t goe using lvcmos1.8 standard ? 0.90 ? 0.90 ? 0.90 ? 0.90 ns l vcmos25_in t in , t gclk_in , t rstb , t goe using lvcmos2.5 standard ? 0.15 ? 0.15 ? 0.15 ? 0.15 ns l vcmos33_in t in , t gclk_in , t rstb , t goe using lvcmos3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns l vttl t in , t gclk_in , t rstb , t goe using lvttl standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_in t in , t gclk_in , t rstb , t goe using pci standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_x_in t in , t gclk_in , t rstb , t goe using pci_x standard ?0.0?0.0? 0.0 ? 0.0 ns a gp_1x_in t in , t gclk_in , t rstb , t goe using agp-1x standard ?0.0?0.0? 0.0 ? 0.0 ns sstl3_i_in t in , t gclk_in , t rstb , t goe using sstl3_i standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl3_ii_in t in , t gclk_in , t rstb , t goe using sstl3_ii standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl2_i_in t in , t gclk_in , t rstb , t goe using sstl2_i standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl2_ii_in t in , t gclk_in , t rstb , t goe using sstl2_ii standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns ctt33_in t in , t gclk_in , t rstb , t goe using ctt3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns ctt25_in t in , t gclk_in , t rstb , t goe using ctt2.5 standard ? 0.15 ? 0.15 ? 0.15 ? 0.15 ns hstl_i_in t in , t gclk_in , t rstb , t goe using hstl_i standard ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns hstl_iii_in t in , t gclk_in , t rstb , t goe using hstl_iii standard ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns gtl+_in t in , t gclk_in , t rstb , t goe using gtl+ standard ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns l vds_in t gclk_in using lvds standard ? 1.70 ? 1.70 ? 1.70 ? 1.70 ns l vpecl_in t gclk_in using lvpecl standard ? 2.10 ? 2.10 ? 2.10 ? 2.10 ns t ioo output adders l vcmos18_4ma_out t buf , t en , t dis output con gured as 1.8v & 4ma buffer ? 3.00 ? 3.00 ? 3.00 ? 3.00 ns l vcmos18_5ma_out t buf , t en , t dis output con gured as 1.8v & 5.33ma buffer ? 2.50 ? 2.50 ? 2.50 ? 2.50 ns l vcmos18_8ma_out t buf , t en , t dis output con gured as 1.8v & 8ma buffer ? 1.85 ? 1.85 ? 1.85 ? 1.85 ns note: open drain timing is the same as corresponding lvcmos timing. timing v.1.20
lattice semiconductor ispmach 5000vg family data sheet 23 l vcmos18_12ma_out t buf , t en , t dis output con gured as 1.8v & 12ma buffer ? 1.35 ? 1.35 ? 1.35 ? 1.35 ns l vcmos25_4ma_out t buf , t en , t dis output con gured as 2.5v & 4ma buffer ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns l vcmos25_5ma_out t buf , t en , t dis output con gured as 2.5v & 5.33ma buffer ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns l vcmos25_8ma_out t buf , t en , t dis output con gured as 2.5v & 8ma buffer ? 0.70 ? 0.70 ? 0.70 ? 0.70 ns l vcmos25_12ma_out t buf , t en , t dis output con gured as 2.5v & 12ma buffer ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns l vcmos25_16ma_out t buf , t en , t dis output con gured as 2.5v & 16ma buffer ? 0.25 ? 0.25 ? 0.25 ? 0.25 ns l vcmos33_4ma_out t buf , t en , t dis output con gured as 3.3v & 4ma buffer ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns l vcmos33_5ma_out t buf , t en , t dis output con gured as 3.3v & 5.33ma buffer ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns l vcmos33_8ma_out t buf , t en , t dis output con gured as 3.3v & 8ma buffer ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns l vcmos33_12ma_out t buf , t en , t dis output con gured as 3.3v & 12ma buffer ? 0.10 ? 0.10 ? 0.10 ? 0.10 ns l vcmos33_16ma_out t buf , t en , t dis output con gured as 3.3v & 16ma buffer ?0.0?0.0? 0.0 ? 0.0 ns l vcmos33_20ma_out t buf , t en , t dis output con gured as 3.3v & 20ma buffer ?0.0?0.0? 0.0 ? 0.0 ns l vttl t buf , t en , t dis output con gured as l vttl buffer ?0.0?0.0? 0.0 ? 0.0 ns slow slew t buf , t en output con gured for slow slew rate ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns pci_out t buf , t en , t dis using pci standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_x_out t buf , t en , t dis using pci-x standard ?0.0?0.0? 0.0 ? 0.0 ns a gp_1x_out t buf , t en , t dis using agp-1x standard ?0.0?0.0? 0.0 ? 0.0 ns sstl3_i_out t buf , t en , t dis using sstl3_i standard ? -0.25 ? -0.25 ? -0.25 ? -0.25 ns sstl3_ii_out t buf , t en , t dis using sstl3_ii standard ? -0.35 ? -0.35 ? -0.35 ? -0.35 ns sstl2_i_out t buf , t en , t dis using sstl2_i standard ?0.0?0.0? 0.0 ? 0.0 ns sstl2_ii_out t buf , t en , t dis using sstl2_ii standard ? -0.25 ? -0.25 ? -0.25 ? -0.25 ns ctt33_out t buf , t en , t dis using cct3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns ctt25_out t buf , t en , t dis using cct2.5 standard ? 0.25 ? 0.25 ? 0.25 ? 0.25 ns hstl_i_out t buf , t en , t dis using hstl_i standard ? -0.30 ? -0.30 ? -0.30 ? -0.30 ns ispmach 5768vg timing adders (continued) adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max note: open drain timing is the same as corresponding lvcmos timing. timing v.1.20
lattice semiconductor ispmach 5000vg family data sheet 24 hstl_iii_out t buf , t en , t dis using hstl_iii standard ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns gtl+_out t buf , t en , t dis using gtl+ standard ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns ispmach 51024vg timing adders adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max t bla t r oute glb loading adder ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns t exp t ptsa pt expander adder ? 1.5 ? 2.0 ? 2.5 ? 2.5 ns t lp t r oute low power adder ? 1.5 ? 1.5 ? 1.5 ? 1.5 ns t ioi input adders l vcmos18_in t in , t gclk_in , t rstb , t goe using lvcmos1.8 standard ? 0.90 ? 0.90 ? 0.90 ? 0.90 ns l vcmos25_in t in , t gclk_in , t rstb , t goe using lvcmos2.5 standard ? 0.15 ? 0.15 ? 0.15 ? 0.15 ns l vcmos33_in t in , t gclk_in , t rstb , t goe using lvcmos3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns l vttl t in , t gclk_in , t rstb , t goe using lvttl standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_in t in , t gclk_in , t rstb , t goe using pci standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_x_in t in , t gclk_in , t rstb , t goe using pci_x standard ?0.0?0.0? 0.0 ? 0.0 ns a gp_1x_in t in , t gclk_in , t rstb , t goe using agp-1x standard ?0.0?0.0? 0.0 ? 0.0 ns sstl3_i_in t in , t gclk_in , t rstb , t goe using sstl3_i standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl3_ii_in t in , t gclk_in , t rstb , t goe using sstl3_ii standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl2_i_in t in , t gclk_in , t rstb , t goe using sstl2_i standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns sstl2_ii_in t in , t gclk_in , t rstb , t goe using sstl2_ii standard ? 1.00 ? 1.00 ? 1.00 ? 1.00 ns ctt33_in t in , t gclk_in , t rstb , t goe using ctt3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns ctt25_in t in , t gclk_in , t rstb , t goe using ctt2.5 standard ? 0.15 ? 0.15 ? 0.15 ? 0.15 ns hstl_i_in t in , t gclk_in , t rstb , t goe using hstl_i standard ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns hstl_iii_in t in , t gclk_in , t rstb , t goe using hstl_iii standard ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns gtl+_in t in , t gclk_in , t rstb , t goe using gtl+ standard ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns note: open drain timing is the same as corresponding lvcmos timing. timing v.1.10 ispmach 5768vg timing adders (continued) adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max note: open drain timing is the same as corresponding lvcmos timing. timing v.1.20
lattice semiconductor ispmach 5000vg family data sheet 25 l vds_in t gclk_in using lvds standard ? 1.70 ? 1.70 ? 1.70 ? 1.70 ns l vpecl_in t gclk_in using lvpecl standard ? 2.10 ? 2.10 ? 2.10 ? 2.10 ns t ioo output adders l vcmos18_4ma_out t buf , t en , t dis output con gured as 1.8v & 4ma buffer ? 3.00 ? 3.00 ? 3.00 ? 3.00 ns l vcmos18_5ma_out t buf , t en , t dis output con gured as 1.8v & 5.33ma buffer ? 2.50 ? 2.50 ? 2.50 ? 2.50 ns l vcmos18_8ma_out t buf , t en , t dis output con gured as 1.8v & 8ma buffer ? 1.85 ? 1.85 ? 1.85 ? 1.85 ns l vcmos18_12ma_out t buf , t en , t dis output con gured as 1.8v & 12ma buffer ? 1.35 ? 1.35 ? 1.35 ? 1.35 ns l vcmos25_4ma_out t buf , t en , t dis output con gured as 2.5v & 4ma buffer ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns l vcmos25_5ma_out t buf , t en , t dis output con gured as 2.5v & 5.33ma buffer ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns l vcmos25_8ma_out t buf , t en , t dis output con gured as 2.5v & 8ma buffer ? 0.70 ? 0.70 ? 0.70 ? 0.70 ns l vcmos25_12ma_out t buf , t en , t dis output con gured as 2.5v & 12ma buffer ? 0.50 ? 0.50 ? 0.50 ? 0.50 ns l vcmos25_16ma_out t buf , t en , t dis output con gured as 2.5v & 16ma buffer ? 0.25 ? 0.25 ? 0.25 ? 0.25 ns l vcmos33_4ma_out t buf , t en , t dis output con gured as 3.3v & 4ma buffer ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns l vcmos33_5ma_out t buf , t en , t dis output con gured as 3.3v & 5.33ma buffer ? 1.25 ? 1.25 ? 1.25 ? 1.25 ns l vcmos33_8ma_out t buf , t en , t dis output con gured as 3.3v & 8ma buffer ? 0.40 ? 0.40 ? 0.40 ? 0.40 ns l vcmos33_12ma_out t buf , t en , t dis output con gured as 3.3v & 12ma buffer ? 0.10 ? 0.10 ? 0.10 ? 0.10 ns l vcmos33_16ma_out t buf , t en , t dis output con gured as 3.3v & 16ma buffer ?0.0?0.0? 0.0 ? 0.0 ns l vcmos33_20ma_out t buf , t en , t dis output con gured as 3.3v & 20ma buffer ?0.0?0.0? 0.0 ? 0.0 ns l vttl t buf , t en , t dis output con gured as l vttl buffer ?0.0?0.0? 0.0 ? 0.0 ns slow slew t buf , t en output con gured for slow slew rate ? 1.50 ? 1.50 ? 1.50 ? 1.50 ns pci_out t buf , t en , t dis using pci standard ? 0.0 ? 0.0 ? 0.0 ? 0.0 ns pci_x_out t buf , t en , t dis using pci-x standard ?0.0?0.0? 0.0 ? 0.0 ns a gp_1x_out t buf , t en , t dis using agp-1x standard ?0.0?0.0? 0.0 ? 0.0 ns sstl3_i_out t buf , t en , t dis using sstl3_i standard ? -0.25 ? -0.25 ? -0.25 ? -0.25 ns sstl3_ii_out t buf , t en , t dis using sstl3_ii standard ? -0.35 ? -0.35 ? -0.35 ? -0.35 ns ispmach 51024vg timing adders (continued) adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max note: open drain timing is the same as corresponding lvcmos timing. timing v.1.10
lattice semiconductor ispmach 5000vg family data sheet 26 sstl2_i_out t buf , t en , t dis using sstl2_i standard ?0.0?0.0? 0.0 ? 0.0 ns sstl2_ii_out t buf , t en , t dis using sstl2_ii standard ? -0.25 ? -0.25 ? -0.25 ? -0.25 ns ctt33_out t buf , t en , t dis using cct3.3 standard ?0.0?0.0? 0.0 ? 0.0 ns ctt25_out t buf , t en , t dis using cct2.5 standard ? 0.25 ? 0.25 ? 0.25 ? 0.25 ns hstl_i_out t buf , t en , t dis using hstl_i standard ? -0.30 ? -0.30 ? -0.30 ? -0.30 ns hstl_iii_out t buf , t en , t dis using hstl_iii standard ? 0.00 ? 0.00 ? 0.00 ? 0.00 ns gtl+_out t buf , t en , t dis using gtl+ standard ? 0.30 ? 0.30 ? 0.30 ? 0.30 ns ispmach 51024vg timing adders (continued) adder t ype base p arameter description -5 -75 -10 -12 units min max min max min max min max note: open drain timing is the same as corresponding lvcmos timing. timing v.1.10
lattice semiconductor ispmach 5000vg family data sheet 27 sysclock pll timing over recommended operating conditions 1 boundary scan timing speci cations symbol parameter conditions min max units t r ,t f input clock, rise and fall time 20% to 80% ? 3.0 ns t instb input clock stability, period jitter (peak) 1 ?? +/- 200 ps t pwh input clock, high time ? 1.6 ? ns t pwl input clock, low time ? 1.6 ? ns f mdivin m divider input, frequency range ? 5 180 mhz f mdivout m divider output, frequency range ? 5 180 mhz f vdivin v divider input, frequency range ? 60 200 mhz f vdivout v divider output, frequency range ? 5 180 mhz t outduty output clock, duty cycle ? 40 60 % t jit(cc) output clock, cycle to cycle jitter (peak) clean reference, 5mhz f mdivout < 80mhz ? +/- 200 ps clean reference, 80mhz f mdivout 180mhz ? +/- 100 ps t jit( ) output clock, accumulated phase jitter (peak) 2 clean reference, 5mhz f mdivout < 80mhz ? +/- 200 ps clean reference, 80mhz f mdivout 180mhz ? +/- 100 ps t clk_out_dly input clock to clk_out delay internal feedback ? 1 ns t input clock to external feedback delta external feedback ? 500 ps t lock time to acquire phase lock after input stable ? ? 30 s t pll_delay delay increment ? +/- 0.35 +/- 0.65 ns t range t otal output delay range ? +/- 2.45 +/- 4.55 ns t pll_rstr reset recovery time of the m-divider ? 11.0 ? ns t pll_rstw minimum reset pulse width ? 6.0 ? ns 1. this condition assures that the output phase jitter (t jit( ) ) will remain within speci cation. 2. accumulated jitter measured over 10,000 waveform samples. symbol parameter min. max. units t btcp tck [bscan test] clock cycle 40 ? ns t btch tck [bscan test] pulse width high 20 ? ns t btcl tck [bscan test] pulse width low 20 ? ns t btsu tck [bscan test] setup time 8 ? ns t bth tck [bscan test] hold time 10 ? ns t brf tck [bscan test] rise and fall time 50 ? mv/ns t btco t ap controller falling edge of clock to valid output ? 10 ns t btoz t ap controller falling edge of clock to data output disable ? 10 ns t btvo t ap controller falling edge of clock to data output enable ? 10 ns t bvtcpsu bscan test capture register setup time 8 ? ns t btcph bscan test capture register hold time 10 ? ns t btuco bscan test update reg, falling edge of clock to valid output ? 25 ns t btuoz bscan test update reg, falling edge of clock to output disable ? 25 ns t btuov bscan test update reg, falling edge of clock to output enable ? 25 ns
lattice semiconductor ispmach 5000vg family data sheet 28 ispmach 5000vg typical power vs. frequency po wer estimation coef cients device k0 k1 k2 k3 k4 k5 k6 i dc (ma) i dco (ma) ispmach 5768vg 0.0014 0.0014 0.054 1.5 0.152 0.105 5.0 65 20 ispmach 51024vg 0.0014 0.0014 0.054 1.5 0.152 0.105 5.0 80 20 note: for further information about the use of these coef cients, refer to technical note tn1002, po w er estimation in ispmach 5000vg devices . k0 = average current per product term in high power/mhz k1 = average current per product term in low power/mhz k2 = average current per grp line/mhz k3 = average current per pll/mhz k4 = dc current per product terms in high power k5 = dc current per product terms in low power k6 = static dc current per pll i dc = static device current with all product terms powered off i dco = static i/o bank current icc estimates are based on typical conditions (vcc = 3.3v, room temperature) and an assumption of one glb load on average exist s. these v alues are for estimates only. since the value of icc is sensitive to operating conditions and the program in the device, the a ctual icc should be veri ed. 100 060 120 150 180 f max (mhz) i cc (ma) note: the devices are configured with maximum number of 16-bit counters, no pll, typical current at 3.3v, 25 c. 300 600 700 500 400 200 0 51024vg high power mode 5768vg high power mode 100 060 120 150 180 f max (mhz) i cc (ma) 300 600 700 500 400 200 0 5768vg low power mode 51024vg low power mode ispmach 5000vg i cc curves at high power mode ispmach 5000vg i cc curves at low power mode po wer consumption
lattice semiconductor ispmach 5000vg family data sheet 29 switching test conditions figure 12 shows the output test load that is used for ac testing. the speci c values for resistance, capacitance, v oltage, and other test conditions are shown in table 3. figure 12. output test load, lvttl and lvcmos standards output test conditions for all other interfaces are determined by the respective standards. for further details, please refer to the following technical note: ? ispmach 5000vg sysio design and usage guidelines (tn1000) ta b le 3. test fixture required components t est condition r 1 r 2 c l timing ref. v cco default lvcmos 3.3 i/o (l -> h, h -> l) 110 110 35pf 1.5 3.0v other lvcmos settings, (l -> h, h -> l) ? 35pf l vcmos 3.3 = 1.5v lvcmos 3.3 = 3.0v l vcmos 2.5 = v cco /2 lvcmos 2.5 = 2.3v l vcmos 1.8 = v cco /2 lvcmos 1.8 = 1.65v default lvcmos 3.3 i/o (z -> h) 110 35pf 1.5v 3.0v default lvcmos 3.3 i/o (z -> l) 110 35pf 1.5v 3.0v default lvcmos 3.3 i/o (h -> z) 110 5pf v oh - 0.3 3.0v default lvcmos 3.3 i/o (l -> z) 110 5pf v ol + 0.3 3.0v v cco r 1 r 2 c l * dut test point * c l includes test fixture and probe capacitance. 0213a/ispm5kvg
lattice semiconductor ispmach 5000vg family data sheet 30 signal descriptions signal names description tms input - this pin is the test mode select input, which is used to control the 1149.1 state machine. tck input - this pin is the test clock input pin, used to clock the 1149.1 state machine. tdi input - this pin is the 1149.1 test data in pin, used to load data. tdo output - this pin is the 1149.1 test data out pin used to shift data out. to e input - test output enable pin. toe tristates all i/o pins when a logic low is driven. goe0, goe1 input - these two pins are the global output enable input pins. resetb dedicated reset input - this pin resets all registers in the devices. the global polarity (active high or low input) for this pin is selectable. xyzz (e.g. 0a16) input/output - these are the general purpose i/o used by the logic array. x is segment reference (numeric), y is glb reference (alpha) and z is macrocell reference (numeric). x : 0-7 (1024) x : 0-5 (768) y : a-d z : 0-31 gnd ground nc no connect v cc vcc - these are the power supply pins for the logic core. gclk0, gclk3 input - these pins are con gured to be either dedicated clk input or pll input. gclk1, gclk2 input - these pins are dedicated clk input. clk_out0, clk_out1 output - these pins are the pll output pins. pll_rst0, pll_rst1 input - these pins are for resetting the pll, input clock (m) divider. vref0, vref1, vref2, vref3 input - these are the reference supplies for the i/o banks. pll_fbk0, pll_fbk1 input - these pll feedback inputs allow optional external pll feedback. v ccp0 , v ccp1 v cc - these are the v cc supplies for the plls. v cco0 , v cco1 , v cco2 , v cco3 v cc - these are the v cc supplies for each i/o bank. gndp0, gndp1 gnd - these are the separate ground connections for the plls. v ccj v cc - this pin is for the 1149.1 test access port. note: for above, signal clk_out0 connects to pll0, and signal clk_out1 connects to pll1.
lattice semiconductor ispmach 5000vg family data sheet 31 ispmach 5768vg power supply and nc connections 1 signal 256-ball fpbga 2 484-ball fpbga 2 v cc f8, f9, h6, h11, j6, j11, l8, l9 b17, b2, b21, b6, c14, c9, e18, e5, f2, f21, j20, j3, p20, p3, u2, u21, y14, y9, aa17, aa2, aa21, aa6 v cco0 c3, c7, g3 b5, d7, e2, e6, e9, f5, g4, j5 v cco1 k3, p3, p7 p5, u5, v6, v9, y3 v cco2 k14, p10, p14 p18, u18, v14, v17, y20 v cco3 c10, c14, g14 b18, d16, e14, e17, e21, f18, g19, j18 v ccp0 h1 l7 v ccp1 h16 n18 v ccj j1 p4 v ref0 e7 a9 v ref1 m7 aa10 v ref2 r13 aa13 v ref3 a8 a15 gnd pll 0 h7 l6 gnd pll 1 j10 l16 gnd a1, c5, c12, e3, e14, g7, g8, g9, g10, h8, h9, h10, j7, j8, j9, k7, k8, k9, k10, m3, m14, p5, p12 a1, a22, c3, c20, d4, d19, e7, e16, g5, g7, g8, g9, g10, g11, g12, g13, g14, g15, g16, g18, h7, h8, h9, h10, h11, h12, h13, h14, h15, h16, j7, j8, j9, j10, j11, j12, j13, j14, j15, j16, k7, k8, k9, k10, k11, k12, k13, k14, k15, k16, l8, l9, l10, l11, l12, l13, l14, l15, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16, t4, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t19, w7, w16, ab1, ab22 nc 3 ? aa1 1. all grounds must be electrically connected at the board level. 2. not all grounds internally connected within the device. 3. nc pins are not to be connected to any active signals, vcc or gnd.
lattice semiconductor ispmach 5000vg family data sheet 32 ispmach 51024 power supply and nc connections 1 signal 484-ball fpbga 2 676-ball fpbga 2 v cc b17, b2, b21, b6, c14, c9, e18, e5, f2, f21, j20, j3, p20, p3, u2, u21, y14, y9, aa17, aa2, aa21, aa6 b29, d6, d10, d12, d19, d21, d25, f4, f27, k4, k27, m4, m27, w4, w27, aa4, aa27, ae4, ae27, ag6, ag10, a g12, ag19, ag21,ag25, aj2 v cco0 b5, d7, e2, e6, e9, f5, g4, j5 e5, e7, e9, e11, f10, g5, j5, k6, l5 v cco1 p5, u5, v6, v9, y3 y5, aa6, ab5, ad5, ae10, af5, af7, af9, af11 v cco2 p18, u18, v14, v17, y20 y26, aa25, ab26, ad26, ae21, af20, af22, af24, af26 v cco3 b18, d16, e14, e17, e21, f18, g19, j18 e20, e22, e24, e26, f21, g26, j26, k25, l26 v ccp0 l7 p5 v ccp1 n18 n26 v ccj p4 u6 v ref0 a9 c11 v ref1 aa10 ak10 v ref2 aa13 aj21 v ref3 a15 e19 gnd pll 0 l6 r6 gnd pll 1 l16 p25 gnd a1, a22, c3, c20, d4, d19, e7, e16, g5, g7, g8, g9, g10, g11, g12, g13, g14, g15, g16, g18, h7, h8, h9, h10, h11, h12, h13, h14, h15, h16, j7, j8, j9, j10, j11, j12, j13, j14, j15, j16, k7, k8, k9, k10, k11, k12, k13, k14, k15, k16, l8, l9, l10, l11, l12, l13, l14, l15, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16, t4, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t19, w7, w16, ab1, ab22 a1, a30, b2,c3, c28, d8, d23, f7, f9, f11, f12, f19, f20, f22, f24, g6, g25, h4, h27, j6, j25, l6, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l25, m6, m11, m12, m13, m14, m15, m16, m17, m18, m19, m20, m25, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, p11, p12, p13, p14, p15, p16, p17, p18, p19, p20, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, u11, u12, u13, u14,u15, u16, u17, u18, u19, u20, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, w6, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, w25, y6, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20, y25, ab6, ab25, ac4, ac27, ad6, ad25, ae7, ae9, ae11, ae12, ae19, ae20, ae22, ae24, ag8, ag23, ah3, ah28, ak1, ak30 nc 3 aa1 a14, a15, a16, a17, b14, b15, b16, b17, c13, c14, c15, c16, c17, c18, d13, d14, d15, d16, d17, d18, e13, e14, e15, e16, e17, e18, f13, f14, f15, f16, f17, f18, ae13, ae14, ae15, ae16, ae17, ae18, af13, af14, af15, af16, af17, af18, ag13, ag14, ag15, a g16, ag17, ag18, ah14, ah15, ah16, ah17, ah18, aj14, aj15, aj16, aj17, aj18, ak14, ak15, ak16, ak17 1. all grounds must be electrically connected at the board level. 2. not all grounds internally connected within the device. 3. nc pins are not to be connected to any active signals, vcc or gnd.
lattice semiconductor ispmach 5000vg family data sheet 33 bank no. signal 256 fpbga 484 fpbga 0 0c-30 c8 d11 0 0c-28 b6 b11 0 0c-26 a5 e12 0 0c-24 d8 c11 0 0c-22 e8 f12 0 0c-20 b5 b10 0 gndio0 gnd gnd 0 0c-18 a4 a10 0 0c-16 d7 d10 0 0c-14/vref0 e7 a9 0 0c-12 c6 e11 0 0c-10 b4 b9 0 0c-8 a3 f11 0 0c-6 nc a8 0 0c-4 nc c10 0 0c-2 nc a7 0 0c-0 nc e10 0 0d-30 nc b8 0 0d-28 nc c8 0 gndio0 gnd gnd 0 0d-26 nc f10 0 0d-24 nc a6 0 0d-22 nc f9 0 0d-20 nc c7 0 0d-18 nc d9 0 0d-16 nc b7 0 0d-14 d6 e8 0 0d-12 e6 a5 0 0d-10 a2 f8 0 0d-8 b3 c6 0 0d-6 c4 d8 0 0d-4 d5 a3 0 gndio0 gnd gnd 0 0d-2 nc a2 0 0d-0 nc a4 0 0a-0 nc f7 0 0a-2 nc c5 0 0a-4 nc f6 0 0a-6 nc b3 0 0a-8 nc nc 0 0a-10 nc nc 0 gndio0 gnd gnd 0 0a-12 nc nc 0 0a-14 nc nc 0 0a-16 nc b4 0 0a-18 nc d5 0 0a-20 nc b1 0 0a-22 nc d6 0 0a-24 nc c4 0 0a-26 nc e4 0 gndio0 gnd gnd 0 0a-28 b2 c2 0 0a-30 b1 c1 0 0b-30 c2 d1 0 0b-28 c1 d2 0 0b-26 nc d3 0 0b-24 nc e1 0 0b-22 nc e3 0 0b-20 nc f4 0 0b-18 nc f1 0 0b-16 nc f3 0 0b-14 nc g6 0 0b-12 nc g1 0 gndio0 gnd gnd 0 0b-10 nc g2 0 0b-8 nc h1 0 0b-6 nc g3 0 0b-4 nc h2 0 0b-2 nc h5 0 0b-0 nc h6 0 1a-0 f7 j1 0 1a-2 f6 k1 0 1a-4 e5 h3 0 1a-6 d4 j2 0 1a-8 d3 h4 0 1a-10 d2 k2 0 gndio0 gnd gnd 0 1a-12 d1 j6 0 1a-14 e4 l1 0 1a-16 nc k3 0 1a-18 nc j4 0 1a-20 nc l2 0 1a-22 nc m1 0 1a-24 nc k6 0 1a-26 nc k4 0 1a-28 nc l3 bank no. signal 256 fpbga 484 fpbga ispmach 5768vg logic signal connections
lattice semiconductor ispmach 5000vg family data sheet 34 0 1a-30 nc k5 0 gndio0 gnd gnd 0 1b-30/clk_out0 g6 n1 0 1b-28 nc m2 0 1b-26 nc p1 0 1b-24 nc l4 0 1b-22 f5 n2 0 1b-20 e2 m3 0 1b-18 e1 l5 0 1b-16 f4 r1 0 1b-14 f3 p2 0 1b-12 f2 n3 0 gndio0 gnd gnd 0 1b-10 g5 m6 0 1b-8 g4 m5 0 1b-6/pll_rst0 f1 m4 0 1b-4/pll_fbk0 g2 n4 0 1b-2 g1 n6 0 1b-0 h5 n5 1 2b-0 k1 r5 1 2b-2 k2 t2 1 2b-4 l1 t5 1 2b-6 j5 t3 1 2b-8 l2 u1 1 2b-10 k4 u4 1 gndio1 gnd gnd 1 2b-12 m1 v1 1 2b-14 l3 u3 1 2b-16 l4 v5 1 2b-18 k5 v2 1 2b-20 m2 w1 1 2b-22 n1 v3 1 2b-24 nc w2 1 2b-26 k6 y1 1 2b-28 l5 y2 1 2b-30 n2 w3 1 2a-30 l6 aa3 1 2a-28 l7 w4 1 gndio1 gnd gnd 1 2a-26 p1 w5 1 2a-24 p2 y4 1 2a-22 n3 t6 1 2a-20 r4 y5 bank no. signal 256 fpbga 484 fpbga 1 2a-18 nc u6 1 2a-16 r1 aa4 1 2a-14 nc nc 1 2a-12 nc nc 1 gndio1 gnd gnd 1 2a-10 nc nc 1 2a-8 nc nc 1 2a-6 t1 w6 1 2a-4 t2 v4 1 2a-2 r2 u7 1 2a-0 t3 ab2 1 2d-0 r3 v7 1 2d-2 p4 aa5 1 gndio1 gnd gnd 1 2d-4 t4 ab3 1 2d-6 n4 y6 1 2d-8 m4 ab4 1 2d-10 n5 y7 1 2d-12 r5 ab5 1 2d-14 t5 v8 1 2d-16 nc aa7 1 2d-18 nc y8 1 2d-20 nc ab6 1 2d-22 t6 w8 1 2d-24 r6 aa8 1 2d-26 p6 y10 1 gndio1 gnd gnd 1 2d-28 m5 u8 1 2d-30 t7 ab7 1 2c-0 t8 u9 1 2c-2 r8 aa9 1 2c-4 m6 w9 1 2c-6 n6 ab8 1 2c-8 r7 u10 1 2c-10 t9 ab9 1 2c-12 t10 v11 1 2c-14/vref1 m7 aa10 1 2c-16 n7 v10 1 2c-18 p8 ab10 1 gndio1 gnd gnd 1 2c-20 r9 w10 1 2c-22 n8 w11 1 2c-24 m8 u11 bank no. signal 256 fpbga 484 fpbga ispmach 5768vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 35 1 2c-26 t11 aa11 1 2c-28 t12 v12 1 2c-30 r10 ab11 2 3c-30 p9 w12 2 3c-28 r11 y11 2 3c-26 t13 y12 2 3c-24 n9 ab12 2 3c-22 m9 u12 2 3c-20 r12 aa12 2 gndio2 gnd gnd 2 3c-18 p11 y13 2 3c-16 n10 ab13 2 3c-14 m10 w13 2 3c-12/vref2 r13 aa13 2 3c-10 t14 u13 2 3c-8 r14 ab14 2 3c-6 m11 v13 2 3c-4 n11 aa14 2 3c-2 p13 u14 2 3c-0 t15 ab15 2 3d-30 t16 y15 2 3d-28 n12 ab16 2 gndio2 gnd gnd 2 3d-26 nc aa15 2 3d-24 nc w14 2 3d-22 nc ab17 2 3d-20 nc y16 2 3d-18 nc aa16 2 3d-16 nc y17 2 3d-14 nc ab18 2 3d-12 nc v15 2 3d-10 nc ab19 2 3d-8 nc w15 2 3d-6 nc ab20 2 3d-4 nc aa18 2 gndio2 gnd gnd 2 3d-2 l10 u15 2 3d-0 l11 w17 2 3a-0 k11 u16 2 3a-2 r15 aa19 2 3a-4 nc v16 2 3a-6 nc ab21 2 3a-8 nc nc bank no. signal 256 fpbga 484 fpbga 2 3a-10 nc nc 2 gndio2 gnd gnd 2 3a-12 nc nc 2 3a-14 nc nc 2 3a-16 nc y18 2 3a-18 p15 w18 2 3a-20 r16 aa20 2 3a-22 p16 w19 2 3a-24 n14 y19 2 3a-26 n13 v19 2 gndio2 gnd gnd 2 3a-28 n15 y21 2 3a-30 n16 w20 2 3b-30 m16 aa22 2 3b-28 m12 w21 2 3b-26 nc y22 2 3b-24 nc v20 2 3b-22 m13 v21 2 3b-20 m15 w22 2 3b-18 l16 v18 2 3b-16 l15 u20 2 3b-14 l13 v22 2 3b-12 l14 u19 2 gndio2 gnd gnd 2 3b-10 l12 u17 2 3b-8 k13 u22 2 3b-6 k15 t20 2 3b-4 k16 t21 2 3b-2 j16 t17 2 3b-0 k12 r20 3 4b-0 j12 r21 3 4b-2 g16 t22 3 4b-4/pll_fbk1 g15 p21 3 4b-6/pll_rst1 h12 n20 3 4b-8 g12 r22 3 4b-10 g13 n21 3 gndio3 gnd gnd 3 4b-12 f16 m18 3 4b-14 f15 n19 3 4b-16 f13 p22 3 4b-18 f14 m20 3 4b-20 f12 n22 3 4b-22 e16 n17 bank no. signal 256 fpbga 484 fpbga ispmach 5768vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 36 3 4b-24 g11 m19 3 4b-26 f11 m21 3 4b-28 f10 l19 3 4b-30/clk_out1 b11 l20 3 gndio3 gnd gnd 3 4a-30 nc m17 3 4a-28 nc m22 3 4a-26 nc k20 3 4a-24 nc l18 3 4a-22 nc l21 3 4a-20 nc k19 3 4a-18 nc l22 3 4a-16 nc k17 3 4a-14 e13 k22 3 4a-12 b12 l17 3 gndio3 gnd gnd 3 4a-10 e15 k21 3 4a-8 d15 k18 3 4a-6 nc j17 3 4a-4 nc j19 3 4a-2 d16 j22 3 4a-0 e12 j21 3 5b-0 nc h19 3 5b-2 nc h20 3 5b-4 nc h17 3 5b-6 nc h18 3 5b-8 nc h22 3 5b-10 nc h21 3 gndio3 gnd gnd 3 5b-12 nc g20 3 5b-14 nc g22 3 5b-16 nc g17 3 5b-18 nc g21 3 5b-20 nc f19 3 5b-22 nc f20 3 5b-24 a16 f22 3 5b-26 b15 e22 3 5b-28 a15 e19 3 5b-30 d13 e20 3 5a-30 b14 d22 3 5a-28 b16 d21 3 gndio3 gnd gnd 3 5a-26 c16 d20 bank no. signal 256 fpbga 484 fpbga 3 5a-24 c15 c22 3 5a-22 d14 c18 3 5a-20 a14 c19 3 5a-18 c13 d17 3 5a-16 b13 c21 3 5a-14 nc nc 3 5a-12 nc nc 3 gndio3 gnd gnd 3 5a-10 nc nc 3 5a-8 nc nc 3 5a-6 nc b22 3 5a-4 nc d18 3 5a-2 nc b20 3 5a-0 nc f17 3 5d-0 nc b19 3 5d-2 nc c17 3 gndio3 gnd gnd 3 5d-4 nc a21 3 5d-6 nc d15 3 5d-8 nc a20 3 5d-10 nc c16 3 5d-12 nc a19 3 5d-14 nc f16 3 5d-16 nc b16 3 5d-18 nc d14 3 5d-20 nc a18 3 5d-22 a13 f15 3 5d-24 a12 a17 3 5d-26 a11 b15 3 gndio3 gnd gnd 3 5d-28 a10 a16 3 5d-30 c11 f14 3 5c-0 a9 c15 3 5c-2 d12 d13 3 5c-4 d11 e15 3 5c-6 b10 f13 3 5c-8 b9 b14 3 5c-10 e11 e13 3 5c-12/vref3 a8 a15 3 5c-14 d10 d12 3 5c-16 e10 a14 3 5c-18 a7 b13 3 gndio3 gnd gnd bank no. signal 256 fpbga 484 fpbga ispmach 5768vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 37 3 5c-20 c9 a13 3 5c-22 e9 b12 3 5c-24 d9 c13 3 5c-26 b8 a12 3 5c-28 a6 c12 3 5c-30 b7 a11 ? gclk0 h4 p6 ? gclk1 j4 r6 ? gclk2 h14 p17 ? gclk3 h13 p19 ? goe0 j15 r18 ? goe1 h15 r17 ? resetb j14 r19 ? tck j3 r3 ? tdi h3 r2 ? tdo j2 r4 ? tms h2 t1 ?toe j13 t18 bank no. signal 256 fpbga 484 fpbga ispmach 5768vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 38 bank no. signal 484 fpbga 676 fpbga 0 0c-30 d11 a13 0 0c-28 b11 b13 0 0c-26 e12 a12 0 0c-24 c11 b12 0 0c-22 f12 c12 0 0c-20 b10 a11 0 gndio0 gnd gnd 0 0c-18 a10 b11 0 0c-16 d10 a10 0 0c-14/vref0 a9 c11 0 0c-12 e11 e12 0 0c-10 b9 b10 0 0c-8 f11 d11 0 0c-6 a8 a9 0 0c-4 c10 c10 0 0c-2 a7 b9 0 0c-0 e10 a8 0 0d-30 b8 c9 0 0d-28 c8 b8 0 gndio0 gnd gnd 0 0d-26 f10 e10 0 0d-24 a6 a7 0 0d-22 f9 d9 0 0d-20 c7 c8 0 0d-18 d9 b7 0 0d-16 b7 a6 0 0d-14 e8 c7 0 0d-12 a5 b6 0 0d-10 f8 a5 0 0d-8 c6 c6 0 0d-6 d8 d7 0 0d-4 a3 e8 0 gndio0 gnd gnd 0 0d-2 a2 b5 0 0d-0 a4 a4 0 0a-0 f7 a3 0 0a-2 c5 b4 0 0a-4 f6 c5 0 0a-6 b3 f8 0 0a-8 nc a2 0 0a-10 nc b3 0 gndio0 gnd gnd 0 0a-12 nc c4 0 0a-14 nc d5 0 0a-16 b4 e6 0 0a-18 d5 d4 0 0a-20 b1 b1 0 0a-22 d6 c2 0 0a-24 c4 f6 0 0a-26 e4 d3 0 gndio0 gnd gnd 0 0a-28 c2 e4 0 0a-30 c1 f5 0 0b-30 d1 c1 0 0b-28 d2 d2 0 0b-26 d3 e3 0 0b-24 e1 d1 0 0b-22 e3 e2 0 0b-20 f4 h6 0 0b-18 f1 f3 0 0b-16 f3 e1 0 0b-14 g6 g4 0 0b-12 g1 f2 0 gndio0 gnd gnd 0 0b-10 g2 h5 0 0b-8 h1 g3 0 0b-6 g3 f1 0 0b-4 h2 g2 0 0b-2 h5 h3 0 0b-0 h6 g1 0 1a-0 j1 h2 0 1a-2 k1 j4 0 1a-4 h3 h1 0 1a-6 j2 j3 0 1a-8 h4 k5 0 1a-10 k2 j2 0 gndio0 gnd gnd 0 1a-12 j6 j1 0 1a-14 l1 k3 0 1a-16 k3 k2 0 1a-18 j4 k1 0 1a-20 l2 l4 0 1a-22 m1 l3 0 1a-24 k6 l2 0 1a-26 k4 m5 0 1a-28 l3 l1 bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections
lattice semiconductor ispmach 5000vg family data sheet 39 0 1a-30 k5 m3 0 gndio0 gnd gnd 0 1b-30/clk_out0 n1 m2 0 1b-28 m2 m1 0 1b-26 p1 n6 0 1b-24 l4 n5 0 1b-22 n2 n4 0 1b-20 m3 n3 0 1b-18 l5 n2 0 1b-16 r1 n1 0 1b-14 p2 p6 0 1b-12 n3 p4 0 gndio0 gnd gnd 0 1b-10 m6 p3 0 1b-8 m5 p2 0 1b-6/pll_rst0 m4 p1 0 1b-4/pll_fbk0 n4 r4 0 1b-2 n6 r3 0 1b-0 n5 r2 1 2b-0 nc r1 1 2b-2 nc t1 1 2b-4 nc t3 1 2b-6 nc t2 1 2b-8 nc u1 1 2b-10 nc u2 1 gndio1 gnd gnd 1 2b-12 nc u3 1 2b-14 nc u4 1 2b-16 nc v1 1 2b-18 nc v2 1 2b-20 nc v3 1 2b-22 nc v4 1 2b-24 nc w1 1 2b-26 nc v6 1 2b-28 nc w2 1 2b-30 nc w3 1 gndio1 gnd gnd 1 2a-30 nc y1 1 2a-28 nc w5 1 2a-26 nc y2 1 2a-24 nc y3 1 2a-22 nc aa1 1 2a-20 nc y4 bank no. signal 484 fpbga 676 fpbga 1 2a-18 nc aa2 1 2a-16 nc aa3 1 2a-14 nc ab1 1 2a-12 nc ab2 1 gndio1 gnd gnd 1 2a-10 nc aa5 1 2a-8 nc ab3 1 2a-6 nc ac1 1 2a-4 nc ab4 1 2a-2 nc ac2 1 2a-0 nc ad1 1 3b-0 r5 ac3 1 3b-2 t2 ad2 1 3b-4 t5 ae1 1 3b-6 t3 ad3 1 3b-8 u1 ae2 1 3b-10 u4 ac5 1 gndio1 gnd gnd 1 3b-12 v1 af1 1 3b-14 u3 ad4 1 3b-16 v5 ae3 1 3b-18 v2 ac6 1 3b-20 w1 af2 1 3b-22 v3 ag1 1 3b-24 w2 af3 1 3b-26 y1 ag2 1 3b-28 y2 ah1 1 3b-30 w3 ae5 1 3a-30 aa3 af4 1 3a-28 w4 ag3 1 gndio1 gnd gnd 1 3a-26 w5 ae6 1 3a-24 y4 ah2 1 3a-22 t6 aj1 1 3a-20 y5 ag4 1 3a-18 u6 af6 1 3a-16 aa4 ag5 1 3a-14 nc ah4 1 3a-12 nc aj3 1 gndio1 gnd gnd 1 3a-10 nc ak2 1 3a-8 nc ae8 1 3a-6 w6 ah5 bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 40 1 3a-4 v4 aj4 1 3a-2 u7 ak3 1 3a-0 ab2 ak4 1 3d-0 v7 aj5 1 3d-2 aa5 ah6 1 gndio1 gnd gnd 1 3d-4 ab3 af8 1 3d-6 y6 ag7 1 3d-8 ab4 ak5 1 3d-10 y7 aj6 1 3d-12 ab5 ah7 1 3d-14 v8 ak6 1 3d-16 aa7 aj7 1 3d-18 y8 ah8 1 3d-20 ab6 ag9 1 3d-22 w8 ak7 1 3d-24 aa8 af10 1 3d-26 y10 aj8 1 gndio1 gnd gnd 1 3d-28 u8 ah9 1 3d-30 ab7 ak8 1 3c-0 u9 aj9 1 3c-2 aa9 ah10 1 3c-4 w9 ak9 1 3c-6 ab8 ag11 1 3c-8 u10 aj10 1 3c-10 ab9 af12 1 3c-12 v11 ah11 1 3c-14/vref1 aa10 ak10 1 3c-16 v10 aj11 1 3c-18 ab10 ak11 1 gndio1 gnd gnd 1 3c-20 w10 ah12 1 3c-22 w11 aj12 1 3c-24 u11 ak12 1 3c-26 aa11 ah13 1 3c-28 v12 aj13 1 3c-30 ab11 ak13 2 4c-30 w12 ak18 2 4c-28 y11 ak19 2 4c-26 y12 aj19 2 4c-24 ab12 ah19 2 4c-22 u12 ak20 bank no. signal 484 fpbga 676 fpbga 2 4c-20 aa12 aj20 2 gndio2 gnd gnd 2 4c-18 y13 ak21 2 4c-16 ab13 ah20 2 4c-14 w13 af19 2 4c-12/vref2 aa13 aj21 2 4c-10 u13 ag20 2 4c-8 ab14 ak22 2 4c-6 v13 ah21 2 4c-4 aa14 aj22 2 4c-2 u14 ak23 2 4c-0 ab15 ah22 2 4d-30 y15 aj23 2 4d-28 ab16 ak24 2 gndio2 gnd gnd 2 4d-26 aa15 af21 2 4d-24 w14 ag22 2 4d-22 ab17 ah23 2 4d-20 y16 aj24 2 4d-18 aa16 ak25 2 4d-16 y17 ah24 2 4d-14 ab18 aj25 2 4d-12 v15 ak26 2 4d-10 ab19 aj26 2 4d-8 w15 ah25 2 4d-6 ab20 ag24 2 4d-4 aa18 af23 2 gndio2 gnd gnd 2 4d-2 u15 ak27 2 4d-0 w17 ak28 2 4a-0 u16 aj27 2 4a-2 aa19 ah26 2 4a-4 v16 ae23 2 4a-6 ab21 ak29 2 4a-8 nc aj28 2 4a-10 nc ah27 2 gndio2 gnd gnd 2 4a-12 nc ag26 2 4a-14 nc af25 2 4a-16 y18 aj29 2 4a-18 w18 ag27 2 4a-20 aa20 aj30 2 4a-22 w19 ah29 bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 41 2 4a-24 y19 ae25 2 4a-26 v19 ag28 2 gndio2 gnd gnd 2 4a-28 y21 af27 2 4a-30 w20 ae26 2 4b-30 aa22 ah30 2 4b-28 w21 ag29 2 4b-26 y22 af28 2 4b-24 v20 ag30 2 4b-22 v21 af29 2 4b-20 w22 ac25 2 4b-18 v18 ae28 2 4b-16 u20 af30 2 4b-14 v22 ad27 2 4b-12 u19 ae29 2 gndio2 gnd gnd 2 4b-10 u17 ac26 2 4b-8 u22 ad28 2 4b-6 t20 ae30 2 4b-4 t21 ad29 2 4b-2 t17 ac28 2 4b-0 r20 ad30 2 5a-0 nc ac29 2 5a-2 nc ab27 2 5a-4 nc ac30 2 5a-6 nc ab28 2 5a-8 nc aa26 2 5a-10 nc ab29 2 gndio2 gnd gnd 2 5a-12 nc ab30 2 5a-14 nc aa28 2 5a-16 nc aa29 2 5a-18 nc aa30 2 5a-20 nc y27 2 5a-22 nc y28 2 5a-24 nc y29 2 5a-26 nc w26 2 5a-28 nc y30 2 5a-30 nc w28 2 gndio2 gnd gnd 2 5b-30 nc w29 2 5b-28 nc w30 2 5b-26 nc v25 bank no. signal 484 fpbga 676 fpbga 2 5b-24 nc v26 2 5b-22 nc v27 2 5b-20 nc v28 2 5b-18 nc v29 2 5b-16 nc v30 2 5b-14 nc u25 2 5b-12 nc u27 2 gndio2 gnd gnd 2 5b-10 nc u28 2 5b-8 nc u29 2 5b-6 nc u30 2 5b-4 nc t27 2 5b-2 nc t28 2 5b-0 nc t29 3 6b-0 r21 t30 3 6b-2 t22 r29 3 6b4/pll_fbk1 p21 r27 3 6b6/pll_rst1 n20 r28 3 6b-8 r22 r30 3 6b-10 n21 p30 3 gndio3 gnd gnd 3 6b-12 m18 p29 3 6b-14 n19 p28 3 6b-16 p22 p27 3 6b-18 m20 n30 3 6b-20 n22 n29 3 6b-22 n17 n28 3 6b-24 m19 n27 3 6b-26 m21 n25 3 6b-28 l19 m30 3 6b-30/clk_out1 l20 m29 3 gndio3 gnd gnd 3 6a-30 m17 m28 3 6a-28 m22 l30 3 6a-26 k20 m26 3 6a-24 l18 l29 3 6a-22 l21 l28 3 6a-20 k19 l27 3 6a-18 l22 k30 3 6a-16 k17 k29 3 6a-14 k22 k28 3 6a-12 l17 j30 3 gndio3 gnd gnd bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 42 3 6a-10 k21 j29 3 6a-8 k18 k26 3 6a-6 j17 j28 3 6a-4 j19 h30 3 6a-2 j22 j27 3 6a-0 j21 h29 3 7b-0 h19 g30 3 7b-2 h20 h28 3 7b-4 h17 g29 3 7b-6 h18 f30 3 7b-8 h22 g28 3 7b-10 h21 h26 3 gndio3 gnd gnd 3 7b-12 g20 f29 3 7b-14 g22 g27 3 7b-16 g17 e30 3 7b-18 g21 f28 3 7b-20 f19 h25 3 7b-22 f20 e29 3 7b-24 f22 d30 3 7b-26 e22 e28 3 7b-28 e19 d29 3 7b-30 e20 c30 3 7a-30 d22 f26 3 7a-28 d21 e27 3 gndio3 gnd gnd 3 7a-26 d20 d28 3 7a-24 c22 f25 3 7a-22 c18 c29 3 7a-20 c19 b30 3 7a-18 d17 d27 3 7a-16 c21 e25 3 7a-14 nc d26 3 7a-12 nc c27 3 gndio3 gnd gnd 3 7a-10 nc b28 3 7a-8 nc a29 3 7a-6 b22 f23 3 7a-4 d18 c26 3 7a-2 b20 b27 3 7a-0 f17 a28 3 7d-0 b19 a27 3 7d-2 c17 b26 bank no. signal 484 fpbga 676 fpbga 3 gndio3 gnd gnd 3 7d-4 a21 e23 3 7d-6 d15 d24 3 7d-8 a20 c25 3 7d-10 c16 a26 3 7d-12 a19 b25 3 7d-14 f16 c24 3 7d-16 b16 a25 3 7d-18 d14 b24 3 7d-20 a18 c23 3 7d-22 f15 d22 3 7d-24 a17 a24 3 7d-26 b15 e21 3 gndio3 gnd gnd 3 7d-28 a16 b23 3 7d-30 f14 c22 3 7c-0 c15 a23 3 7c-2 d13 b22 3 7c-4 e15 c21 3 7c-6 f13 a22 3 7c-8 b14 d20 3 7c-10 e13 b21 3 7c-12/vref3 a15 e19 3 7c-14 d12 c20 3 7c-16 a14 a21 3 7c-18 b13 b20 3 gndio3 gnd gnd 3 7c-20 a13 a20 3 7c-22 b12 c19 3 7c-24 c13 b19 3 7c-26 a12 a19 3 7c-28 c12 b18 3 7c-30 a11 a18 ? gclk0 p6 r5 ? gclk1 r6 t6 ? gclk2 p17 r25 ? gclk3 p19 p26 ? goe0 r18 t26 ? goe1 r17 r26 ? resetb r19 t25 ? tck r3 u5 ? tdi r2 t5 ? tdo r4 v5 bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 43 ? tms t1 t4 ?toe t18 u26 bank no. signal 484 fpbga 676 fpbga ispmach 51024vg logic signal connections (continued)
lattice semiconductor ispmach 5000vg family data sheet 44 signal con guration ispmach 5768vg 256-ball fpbga i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd vcco3 vcco3 vcco0 vcco1 vcco3 vcco0 vcco0 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd vcco2 vcco2 vcco1 vcco1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccp0 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc vcc i/o i/o i/o i/o i/o tdi vcc vcc vcc vcc vccp1 resetb gclk2 goe1 goe0 gclk1 tck tdo vccj vcco2 toe gndp0 gndp1 tms i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc vcc gnd gnd gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o/ vref3 i/o/ clk_out1 i/o/ pll_fbk1 i/o/ pll_fbk0 i/o/ pll_rst1 i/o/ vref1 i/o/ vref2 i/o/ clk_out0 gclk0 gclk3 i/o/ vref0 i/o/ pll_rst0 1 a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 256fpbga/5768vg note: ball a1 indicator dot on top side of package. ispmach 5768vg bottom view
lattice semiconductor ispmach 5000vg family data sheet 45 signal con guration ispmach 5768vg and 51024vg 484-ball fpbga i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ vref0 i/o / vref3 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc vcc vcc vcc gnd vcc vcc vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ clk_out1 i/o/ pll_rst1 i/o/ pll_fbk1 i/o i/o i/o gndp1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc vcc vcc vcc i/o i/o i/o i/o i/o tdo tck tdi i/o i/o gnd goe0 goe1 toe i/o gnd gnd gnd gnd gnd gnd gnd gnd tms gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcco2 vccp1 vcco2 gclk3 gclk2 gclk0 gclk1 vcco3 vcco3 vcco3 vcco3 vcco3 vcco3 vcco3 vcco3 vcco2 resetb vcco2 vcco1 vcco1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ clk_out0 i/o/ pll_fbk0 i/o i/o i/o/ pll_rst0 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o vcco2 i/o i/o i/o i/o i/o vcc i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o vcco1 vccj vcco1 vcco1 vcco0 vcco0 vcco0 vcco0 vcco0 vcco0 vcco0 vcco0 gndp0 vccp0 i/o i/o i/o vcc vcc i/o i/o i/o vcc i/o i/o i/o i/o/ vref2 i/o/ vref1 i/o i/o i/o i/o i/o vcc i/o i/o i/o vcc vcc nc 1 gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd 1 a b c d e f g h j k l m n p r t u v w y aa ab a b c d e f g h j k l m n p r t u v w y aa ab 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 484bga/51024vg 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. ispmach 5768vg and 51024vg bottom view
lattice semiconductor ispmach 5000vg family data sheet 46 signal con guration ispmach 51024vg 676-ball fpbga 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 a gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd a b i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o b c i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ vref0 i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o c d i/o i/o i/o i/o i/o vcc i/o gnd i/o vcc i/o vcc vcc i/o vcc i/o gnd i/o vcc i/o i/o i/o i/o i/o d e i/o i/o i/o i/o vcco3 i/o vcco3 i/o vcco3 i/o vcco3 i/o/ vref3 i/o vcco0 i/o vcco0 i/o vcco0 i/o vcco0 i/o i/o i/o i/o e f i/o i/o i/o vcc i/o i/o i/o vcco3 gnd gnd gnd gnd gnd gnd gnd gnd vcco0 i/o i/o i/o vcc i/o i/o i/o f g i/o i/o i/o i/o vcco3 vcco0 i/o i/o i/o i/o g h i/o i/o i/o gnd gnd gnd gnd gnd gnd gnd i/o i/o i/o i/o gnd i/o i/o i/o h j i/o i/o i/o i/o vcco3 vcco0 i/o i/o i/o i/o j k i/o i/o i/o vcc i/o vcco3 vcco0 i/o vcc i/o i/o i/o k l i/o i/o i/o i/o vcco3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcco0 i/o i/o i/o i/o l m i/o i/o/ c lk_out1 i/o vcc i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o vcc i/o i/o/ c lk_out 0 i/o m n i/o i/o i/o i/o vccp1 i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o i/o i/o i/o i/o i/o n p i/o i/o i/o i/o gclk3 gndp1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o v ccp0 i/o i/o i/o/ pll_rst0 p r i/o i/o i/o/ pll_rst1 i/o/ p ll_fbk1 goe1 gclk2 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gndp0 gclk0 i/o/ pll_fbk0 i/o i/o r t i/o i/o i/o i/o goe0 r eset b gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd tdi gclk1 tms t u i/o i/o i/o i/o toe i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vccj tck i/o i/o i/o i/o i/o i/o i/o i/o u v i/o i/o i/o i/o i/o i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o tdo i/o i/o i/o i/o v w i/o i/o i/o vcc i/o gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o vcc i/o i/o i/o w y i/o i/o i/o i/o vcco2 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcco1 i/o i/o i/o i/o y aa i/o i/o i/o vcc i/o vcco2 vcco1 i/o vcc i/o i/o i/o aa ab i/o i/o i/o i/o vcco2 vcco1 i/o i/o i/o i/o ab ac i/o i/o i/o gnd i/o i/o i/o i/o gnd gnd gnd gnd gnd gnd gnd i/o i/o i/o ac ad i/o i/o i/o i/o vcco2 vcco1 i/o i/o i/o i/o ad ae i/o i/o i/o vcc i/o i/o i/o vcco2 gnd gnd gnd gnd gnd gnd gnd nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 nc 1 gnd vcco1 i/o i/o i/o vcc i/o i/o i/o ae af i/o i/o i/o i/o vcco2 i/o vcco2 i/o vcco2 i/o vcco2 i/o i/o vcco1 i/o vcco1 i/o vcco1 i/o vcco1 i/o i/o i/o i/o af ag i/o i/o i/o i/o i/o vcc i/o gnd i/o vcc i/o vcc vcc i/o vcc i/o gnd i/o vcc i/o i/o i/o i/o i/o ag ah i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o ah aj i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ vref2 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc i/o aj ak gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o/ vref1 i/o i/o i/o i/o i/o i/o i/o i/o gnd 676bga/51024vg ak 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 i/o 1. ncs are not to be connected to any active signals, vcc or gnd. note: ball a1 indicator dot on top side of package. ispmach 51024vg bottom view
lattice semiconductor ispmach 5000vg family data sheet 47 pa rt number description ordering information commercial pa rt number package pin count macrocells tpd voltage lc51024vg-5f484c fpbga 484 1024 5 3.3 lc51024vg-75f484c fpbga 484 1024 7.5 3.3 lc51024vg-10f484c fpbga 484 1024 10 3.3 lc51024vg-5f676c fpbga 676 1024 5 3.3 lc51024vg-75f676c fpbga 676 1024 7.5 3.3 lc51024vg-10f676c fpbga 676 1024 10 3.3 lc5768vg-5f256c fpbga 256 768 5 3.3 lc5768vg-75f256c fpbga 256 768 7.5 3.3 lc5768vg-10f256c fpbga 256 768 10 3.3 lc5768vg-5f484c fpbga 484 768 5 3.3 lc5768vg-75f484c fpbga 484 768 7.5 3.3 lc5768vg-10f484c fpbga 484 768 10 3.3 note: the ispmach 5000vg family is dual-marked with both commercial and industrial grades. the commercial speed grade is one speed grade faster (i.e. lc51024vg-75f484c ) than the industrial speed grade (i.e. lc51024vg-10f484i). device number 5768 = 768 macrocells 51024 = 1,024 macrocells lc xxxxxvg ? xx fxxx x xx device status blank = final production es = engineering samples speed 5 = 5.0ns 75 = 7.5ns 10 = 10ns 12 = 12ns* *industrial grade only. package f256 = 256-ball fpbga f484 = 484-ball fpbga f676 = 676-ball fpbga grade c = commercial i = industrial device family 0212/ispm5vg
lattice semiconductor ispmach 5000vg family data sheet 48 industrial for further information in addition to this data sheet, the following technical notes may be helpful when designing with the ispmach 5000vg family: ? ispmach 5000vg sysio design and usage guidelines (tn1000) ? ispmach 5000vg timing model design and usage guidelines (tn1001) ? po w er estimation in ispmach 5000vg devices (tn1002) ? ispmach 5000vg pll usage guidelines (tn1003) pa rt number package pin count macrocells tpd voltage lc51024vg-75f484i fpbga 484 1024 7.5 3.3 lc51024vg-10f484i fpbga 484 1024 10 3.3 lc51024vg-12f484i fpbga 484 1024 12 3.3 lc51024vg-75f676i fpbga 676 1024 7.5 3.3 lc51024vg-10f676i fpbga 676 1024 10 3.3 lc51024vg-12f676i fpbga 676 1024 12 3.3 lc5768vg-75f256i fpbga 256 768 7.5 3.3 lc5768vg-10f256i fpbga 256 768 10 3.3 lc5768vg-12f256i fpbga 256 768 12 3.3 lc5768vg-75f484i fpbga 484 768 7.5 3.3 LC5768VG-10F484I fpbga 484 768 10 3.3 lc5768vg-12f484i fpbga 484 768 12 3.3 note: the ispmach 5000vg family is dual-marked with both commercial and industrial grades. the commercial speed grade is one speed grade faster (i.e. lc51024vg-75f484c ) than the industrial speed grade (i.e. lc51024vg-10f484i).

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